数据搜索系统,热门电子元器件搜索
  Chinese▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

EBE51ED8AEFA-6 Datasheet(数据表) 12 Page - Elpida Memory

部件型号  EBE51ED8AEFA-6
说明  512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
下载  22 Pages
Scroll/Zoom Zoom In 100% Zoom Out
制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51ED8AEFA-6 Datasheet(HTML) 12 Page - Elpida Memory

Back Button EBE51ED8AEFA-6 数据表 HTML 8Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 9Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 10Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 11Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 12Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 13Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 14Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 15Page - Elpida Memory EBE51ED8AEFA-6 数据表 HTML 16Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 12 page
background image
EBE51ED8AEFA-6
Data Sheet E0724E10 (Ver. 1.0)
12
Parameter
Symbol
Grade
max.
Unit
Test condition
Self-refresh current
IDD6
54
mA
Self Refresh Mode;
CK and /CK at 0V;
CKE
≤ 0.2V;
Other control and address bus inputs are FLOATING;
Data bus inputs are FLOATING
Operating current
(Bank interleaving)
IDD7
2880
mA
all bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD (IDD)
−1
× tCK (IDD);
tCK = tCK (IDD), tRC = tRC (IDD), tRRD = tRRD(IDD),
tRCD = 1
× tCK (IDD);
CKE is H, CS is H between valid commands;
Address bus inputs are STABLE during DESELECTs;
Data pattern is same as IDD4W;
Notes: 1. IDD specifications are tested after the device is properly initialized.
2. Input slew rate is specified by AC Input Test Condition.
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, /DQS, RDQS, /RDQS, LDQS, /LDQS, UDQS, and /UDQS. IDD
values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
L is defined as VIN
≤ VIL (AC) (max.)
H is defined as VIN
≥ VIH (AC) (min.)
STABLE is defined as inputs stable at an H or L level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between H and L every other clock cycle (once per two clocks) for address and control
signals, and inputs changing between H and L every other data transfer (once per clock) for DQ signals
not including masks or strobes.
6. Refer to AC Timing for IDD Test Conditions.
AC Timing for IDD Test Conditions
For purposes of IDD testing, the following parameters are to be utilized.
DDR2-667
Parameter
5-5-5
Unit
CL(IDD)
5
tCK
tRCD(IDD)
15
ns
tRC(IDD)
60
ns
tRRD(IDD)
7.5
ns
tCK(IDD)
3
ns
tRAS(min.)(IDD)
45
ns
tRAS(max.)(IDD)
70000
ns
tRP(IDD)
15
ns
tRFC(IDD)
105
ns




HTML 页

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22 


数据表 下载

Go To PDF Page


链接网址


Privacy Policy
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ]  

关于 Alldatasheet    |   广告服务   |   联系我们   |   隐私政策   |   书签   |   链接交换   |   制造商名单
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl