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EBE51ED8ABFA Datasheet(数据表) 5 Page - Elpida Memory

部件型号  EBE51ED8ABFA
说明  512MB Unbuffered DDR2 SDRAM DIMM (64M words x 72 bits, 1 Rank)
下载  22 Pages
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制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBE51ED8ABFA Datasheet(HTML) 5 Page - Elpida Memory

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EBE51ED8ABFA
Data Sheet E0378E40 (Ver. 4.0)
5
Serial PD Matrix
Byte No.
Function described
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Hex value
Comments
0
Number of bytes utilized by module
manufacturer
1
0
0
0
0
0
0
0
80H
128 bytes
1
Total number of bytes in serial PD
device
0
0
0
0
1
0
0
0
08H
256 bytes
2
Memory type
0
0
0
0
1
0
0
0
08H
DDR2 SDRAM
3
Number of row address
0
0
0
0
1
1
1
0
0EH
14
4
Number of column address
0
0
0
0
1
0
1
0
0AH
10
5
Number of DIMM ranks
0
1
1
0
0
0
0
0
60H
1
6
Module data width
0
1
0
0
1
0
0
0
48H
72
7
Module data width continuation
0
0
0
0
0
0
0
0
00H
0
8
Voltage interface level of this assembly 0
0
0
0
0
1
0
1
05H
SSTL 1.8V
9
DDR SDRAM cycle time, CL = 5
-5C
0
0
1
1
1
1
0
1
3DH
3.75ns*
1
-4A
0
1
0
1
0
0
0
0
50H
5.0ns*
1
10
SDRAM access from clock (tAC)
-5C
0
1
0
1
0
0
0
0
50H
0.5ns*
1
-4A
0
1
1
0
0
0
0
0
60H
0.6ns*
1
11
DIMM configuration type
0
0
0
0
0
0
1
0
02H
ECC
12
Refresh rate/type
1
0
0
0
0
0
1
0
82H
7.8
µs
13
Primary SDRAM width
0
0
0
0
1
0
0
0
08H
× 8
14
Error checking SDRAM width
0
0
0
0
1
0
0
0
08H
× 8
15
Reserved
0
0
0
0
0
0
0
0
00H
0
16
SDRAM device attributes:
Burst length supported
0
0
0
0
1
1
0
0
0CH
4,8
17
SDRAM device attributes: Number of
banks on SDRAM device
0
0
0
0
0
1
0
0
04H
4
18
SDRAM device attributes:
/CAS latency
0
0
1
1
1
0
0
0
38H
3, 4, 5
19
Reserved
0
0
0
0
0
0
0
0
00H
0
20
DIMM type information
0
0
0
0
0
0
1
0
02H
Unbuffered
21
SDRAM module attributes
0
0
0
0
0
0
0
0
00H
Normal
22
SDRAM device attributes: General
0
0
1
1
0
0
0
0
30H
VDD ± 0.1V
23
Minimum clock cycle time at CL = 4
-5C
0
0
1
1
1
1
0
1
3DH
3.75ns*
1
-4A
0
1
0
1
0
0
0
0
50H
5.0ns*
1
24
Maximum data access time (tAC) from
clock at CL = 4
-5C
0
1
0
1
0
0
0
0
50H
0.5ns*
1
-4A
0
1
1
0
0
0
0
0
60H
0.6ns*
1
25
Minimum clock cycle time at CL = 3
-5C, -4A
0
1
0
1
0
0
0
0
50H
5.0ns*
1
26
Maximum data access time (tAC) from
clock at CL = 3
-5C, -4A
0
1
1
0
0
0
0
0
60H
0.6ns*
1




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