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EBE21RD4AGFA 数据表(PDF) 1 Page - Elpida Memory |
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EBE21RD4AGFA 数据表(HTML) 1 Page - Elpida Memory |
1 / 23 page Document No. E0794E20 (Ver. 2.0) Date Published October 2005 (K) Japan Printed in Japan URL: http://www.elpida.com Elpida Memory, Inc. 2005 DATA SHEET 2GB Registered DDR2 SDRAM DIMM EBE21RD4AGFA (256M words × 72 bits, 2 Ranks) Description The EBE21RD4AGFA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM sealed in FBGA ( µBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This high- speed data transfer is realized by the 4bits prefetch- pipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA ( µBGA) on the module board. Note: Do not push the cover or drop the modules in order to avoid mechanical defects, which may result in electrical defects. Features • 240-pin socket type dual in line memory module (DIMM) PCB height: 30.0mm Lead pitch: 1.0mm Lead-free (RoHS compliant) • Power supply: VDD = 1.8V ± 0.1V • Data rate: 667Mbps/533Mbps/400Mbps (max.) • SSTL_18 compatible I/O • Double-data-rate architecture: two data transfers per clock cycle • Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in capturing data at the receiver • DQS is edge aligned with data for READs; center aligned with data for WRITEs • Differential clock inputs (CK and /CK) • DLL aligns DQ and DQS transitions with CK transitions • Commands entered on each positive CK edge; data referenced to both edges of DQS • Four internal banks for concurrent operation (components) • Burst length: 4, 8 • /CAS latency (CL): 3, 4, 5 • Auto precharge option for each burst access • Auto refresh and self refresh modes • Average refresh period 7.8µs at 0°C ≤ TC ≤ +85°C 3.9µs at +85°C < TC ≤ +95°C • Posted CAS by programmable additive latency for better command and data bus efficiency • Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality • /DQS can be disabled for single-ended Data Strobe operation • 1 piece of PLL clock driver, 4 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD) |
类似零件编号 - EBE21RD4AGFA |
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类似说明 - EBE21RD4AGFA |
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