EBD52UD6ADSA-E datasheet(1/19 Pages) ELPIDA

部件名	EBD52UD6ADSA-E

功能描述	512MB DDR SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)

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制造商	ELPIDA [Elpida Memory]

网页	http://www.elpida.com/en

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Document No. E0604E10 (Ver. 1.0)

Date Published October 2004 (K) Japan

URL: http://www.elpida.com

Elpida Memory , Inc. 2004

DATA SHEET

512MB DDR SDRAM SO-DIMM

EBD52UD6ADSA-E (64M words

× 64 bits, 2 Ranks)

Description

The EBD52UD6ADSA is 64M words

× 64 bits, 2 ranks

Double Data Rate (DDR) SDRAM Small Outline Dual

In-line Memory Module, mounting 8 pieces of 512M

bits DDR SDRAM sealed in TSOP package. Read and

write operations are performed at the cross points of

the CK and the /CK. This high-speed data transfer is

realized by the 2 bits prefetch-pipelined architecture.

Data strobe (DQS) both for read and write are available

for high speed and reliable data bus design. By setting

extended mode register, the on-chip Delay Locked

Loop (DLL) can be set enable or disable. This module

provides high density mounting without utilizing surface

mount technology. Decoupling capacitors are mounted

beside each TSOP on the module board.

Features

• 200-pin socket type small outline dual in line memory

module (SO-DIMM)

 PCB height: 31.75mm

 Lead pitch: 0.6mm

 Lead-free

• 2.5V power supply

• Data rate: 333Mbps/266Mbps (max.)

• 2.5 V (SSTL_2 compatible) I/O

• Double Data Rate architecture; two data transfers per

clock cycle

• Bi-directional, data strobe (DQS) is transmitted

/received with data, to be used in capturing data at

the receiver

• Data inputs, outputs and DM are synchronized with

DQS

• 4 internal banks for concurrent operation

(Components)

• DQS is edge aligned with data for READs; center

aligned with data for WRITEs

• Differential clock inputs (CK and /CK)

• DLL aligns DQ and DQS transitions with CK

transitions

• Commands entered on each positive CK edge; data

referenced to both edges of DQS

• Data mask (DM) for write data

• Auto precharge option for each burst access

• Programmable burst length: 2, 4, 8

• Programmable /CAS latency (CL): 2, 2.5

• Refresh cycles: (8192 refresh cycles /64ms)

 7.8µs maximum average periodic refresh interval

• 2 variations of refresh

 Auto refresh

 Self refresh

类似零件编号 - EBD52UD6ADSA-E

制造商	部件名	数据表	功能描述
Elpida Memory	EBD52UD6ADSA-6B	253Kb / 19P	512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
	EBD52UD6ADSA-7A	253Kb / 19P	512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
	EBD52UD6ADSA-7B	253Kb / 19P	512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)

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类似说明 - EBD52UD6ADSA-E

制造商	部件名	数据表	功能描述
Elpida Memory	EBD52UC8AKDA	199Kb / 19P	512MB DDR SDRAM SO DIMM (64M words x 64 bits, 2 Ranks)
	EBD52UD6ADSA	253Kb / 19P	512MB DDR SDRAM SO-(64M words x 64 bits, 2 Ranks)
	EBE52UD6ABSA	229Kb / 21P	512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
	EBD52UC8AKFA-5-E	190Kb / 19P	512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks)
	EBE52UD6AFSA	254Kb / 23P	512MB DDR2 SDRAM SO-DIMM (64M words x 64 bits, 2 Ranks)
	EBD52UC8AKFA-5	152Kb / 19P	512MB Unbuffered DDR SDRAM DIMM (64M words x 64 bits, 2 Ranks)
	EBD52EC8AKFA-5	179Kb / 19P	512MB Unbuffered DDR SDRAM DIMM (64M words x 72 bits, 2 Ranks)
	EBD26UC6AKSA-E	213Kb / 19P	256MB DDR SDRAM SO-DIMM (32M words x 64 bits, 2 Ranks)
	EBD11UD8ADDA-E	216Kb / 19P	1GB DDR SDRAM SO-DIMM (128M words x64 bits, 2 Ranks)
	EBE11UD8AESA	214Kb / 22P	1GB DDR2 SDRAM SO-DIMM (128M words x 64 bits, 2 Ranks)

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EBD52UD6ADSA-E 数据表(PDF) 1 Page - Elpida Memory

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