数据搜索系统,热门电子元器件搜索
  Chinese▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

EBD51RC4AKFA Datasheet(数据表) 1 Page - Elpida Memory

部件型号  EBD51RC4AKFA
说明  512MB Registered DDR SDRAM DIMM (64M words X 72 bits, 1 Rank)
下载  19 Pages
Scroll/Zoom Zoom In 100% Zoom Out
制造商  ELPIDA [Elpida Memory]
网页  http://www.elpida.com/en
标志 ELPIDA - Elpida Memory

EBD51RC4AKFA Datasheet(HTML) 1 Page - Elpida Memory

  EBD51RC4AKFA 数据表 HTML 1Page - Elpida Memory EBD51RC4AKFA 数据表 HTML 2Page - Elpida Memory EBD51RC4AKFA 数据表 HTML 3Page - Elpida Memory EBD51RC4AKFA 数据表 HTML 4Page - Elpida Memory EBD51RC4AKFA 数据表 HTML 5Page - Elpida Memory EBD51RC4AKFA 数据表 HTML 6Page - Elpida Memory EBD51RC4AKFA 数据表 HTML 7Page - Elpida Memory EBD51RC4AKFA 数据表 HTML 8Page - Elpida Memory EBD51RC4AKFA 数据表 HTML 9Page - Elpida Memory Next Button
Zoom Inzoom in Zoom Outzoom out
 1 page
background image
Document No. E0377E20 (Ver. 2.0)
Date Published January 2004 (K) Japan
URL: http://www.elpida.com
Elpida Memory,Inc. 2003-2004
DATA SHEET
512MB Registered DDR SDRAM DIMM
EBD51RC4AKFA (64M words
×××× 72 bits, 1 Rank)
Description
The EBD51RC4AKFA is a 64M words
× 72 bits, 1 rank
Double Data Rate (DDR) SDRAM Module, mounting 18
pieces of DDR SDRAM sealed in TSOP package.
Read and write operations are performed at the cross
points of the CK and the /CK. This high-speed data
transfer is realized by the 2-bit prefetch-pipelined
architecture.
Data strobe (DQS) both for read and
write are available for high speed and reliable data bus
design. By setting extended mode register, the on-chip
Delay Locked Loop (DLL) can be set enable or disable.
This module provides high density mounting without
utilizing surface mount technology.
Decoupling
capacitors are mounted beside each TSOP on the
module board.
Features
• 184-pin socket type dual in line memory module
(DIMM)
 PCB height: 30.48mm
 Lead pitch: 1.27mm
• 2.5V power supply
• Data rate: 333Mbps/266Mbps (max.)
• 2.5 V (SSTL_2 compatible) I/O
• Double Data Rate architecture; two data transfers per
clock cycle
• Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
• Data inputs and outputs are synchronized with DQS
• 4 internal banks for concurrent operation
(Component)
• DQS is edge aligned with data for READs; center
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge; data
referenced to both edges of DQS
• Auto precharge option for each burst access
• Programmable burst length: 2, 4, 8
• Programmable /CAS latency (CL): 2, 2.5
• Refresh cycles: (8192 refresh cycles /64ms)
 7.8µs maximum average periodic refresh interval
• 2 variations of refresh
 Auto refresh
 Self refresh
• 1 piece of PLL clock driver, 2 pieces of register
drivers and 1 piece of serial EEPROM (2k bits
EEPROM) for Presence Detect (PD)




HTML 页

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19 


数据表 下载

Go To PDF Page


链接网址


Privacy Policy
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ]  

关于 Alldatasheet    |   广告服务   |   联系我们   |   隐私政策   |   书签   |   链接交换   |   制造商名单
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl