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PDAC11001APFBT 数据表(PDF) 13 Page - Texas Instruments |
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PDAC11001APFBT 数据表(HTML) 13 Page - Texas Instruments |
13 / 42 page 13 DAC11001A, DAC91001, DAC81001 www.ti.com SLASEL0 – OCTOBER 2019 Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 7.9 Timing Requirements: Read and Daisy-Chain Write, 2.7 V ≤ DV DD < 4.5 V all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCLK frequency 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 8 MHz 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 16 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 10 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 20 tSCLKHIG H SCLK high time 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 62 ns 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 31 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 50 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 25 tSCLKLO W SCLK low time 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 62 ns 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 31 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 50 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 25 tSDIS SDI setup, 1.7 V ≤ IOVDD < 2.7 V 21 ns SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V 16 tSDIH SDI hold, 1.7 V ≤ IOVDD < 2.7 V 21 ns SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V 16 tCSS SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V 41 ns SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 36 tCSH SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V 25 ns SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tCSHIGH SYNC high time, 1.7 V ≤ IOVDD < 2.7 V 100 ns SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V 100 tCSIGNO RE SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V 10 ns SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V 5 tLDACSL Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V 100 ns Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 100 tLDACW LDAC low time, 1.7 V ≤ IOVDD < 2.7 V 40 ns LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V 40 tCLRW CLR low time, 1.7 V ≤ IOVDD < 2.7 V 40 ns CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V 40 tSDODLY SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 0 40 ns SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 0 30 SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 0 40 SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 0 30 tSDOZ SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V 0 20 ns SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V 0 20 |
类似零件编号 - PDAC11001APFBT |
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类似说明 - PDAC11001APFBT |
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