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DAC53401_V01 Datasheet(数据表) 11 Page - Texas Instruments

部件型号  DAC53401
说明  DACx3401 10-Bit and 8-Bit, Voltage-Output Digital-to-Analog Converters With Nonvolatile Memory and PMBus™ Compatible I2C Interface in Tiny 2 × 2 WSON
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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DAC53401 Datasheet(HTML) 11 Page - Texas Instruments

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11
DAC53401, DAC43401
www.ti.com
SLASES7 – JULY 2019
Product Folder Links: DAC53401 DAC43401
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Feature Description (continued)
8.3.2 DAC Update
The DAC output pin (OUT) is updated at the end of I2C DAC write frame.
8.3.2.1 DAC Update Busy
The DAC_UPDATE_BUSY bit (address D0h) is set to 1 by the device when certain DAC update operations, such
as function generation, transition to margin high or low, or any of the medical alarms are in progress. When the
DAC_UPDATE_BUSY bit is set to 1, do not write to any of the DAC registers. After the DAC update operation is
completed (DAC_UPDATE_BUSY = 0), any of the DAC registers can be written.
8.3.3 Nonvolatile Memory (EEPROM or NVM)
The DACx3401 contains nonvolatile memory (NVM) bits. These memory bits are user programmable and
erasable, and retain the set values in the absence of a power supply. All the register bits, as shown in Table 1,
can be stored in the device NVM by setting NVM_PROG = 1 (address D3h). The NVM_BUSY bit (address D0h)
is set to 1 by device when a NVM write or reload operation is ongoing. During this time, the device blocks all
write operations to the device. The NVM_BUSY bit is set to 0 after the write or reload operation is complete; at
this point, all write operations to the device are allowed. The default value for all the registers in the DACx3401 is
loaded from NVM as soon as a POR event is issued. Do not perform a read operation from the DAC register
while NVM_BUSY = 1.
The DACx3401 also implements NVM_RELOAD bit (address D3h). Set this bit to 1 for the device to start an
NVM reload operation. After the operation is complete, the device autoresets this bit to 0. During the
NVM_RELOAD operation, the NVM_BUSY bit is set to 1.
Table 1. NVM Programmable Registers
REGISTER ADDRESS
REGISTER NAME
BIT ADDRESS
BIT NAME
D1h
GENERAL_CONFIG
15:14
FUNC_CONFIG
13
DEVICE_LOCK
11:9
CODE_STEP
8:5
SLEW_RATE
4:3
DAC_PDN
2
REF_EN
1:0
DAC_SPAN
D2h
MED_ALARM_CONFIG
10
MED_ALARM_HP
9
MED_ALARM_MP
8
MED_ALARM_LP
5:4
INTERBURST_TIME
3:2
PULSE_OFF_TIME
1:0
PULSE_ON_TIME
D3h
TRIGGER
8
START_FUNC_GEN
10h
DAC_DATA
11:2
DAC_DATA
25h
DAC_MARGIN_HIGH
11:4
MARGIN_HIGH (8 most significant bits)
26h
DAC_MARGIN_LOW
11:4
MARGIN_LOW (8 most significant bits)




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