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DAC11001A 数据表(PDF) 12 Page - Texas Instruments |
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DAC11001A 数据表(HTML) 12 Page - Texas Instruments |
12 / 42 page 12 DAC11001A, DAC91001, DAC81001 SLASEL0 – OCTOBER 2019 www.ti.com Product Folder Links: DAC11001A DAC91001 DAC81001 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated 7.8 Timing Requirements: Read and Daisy-Chain Write, 4.5 V ≤ DV DD ≤ 5.5 V all input signals are specified with tR = tF = 1 ns/V (10% to 90% of IOVDD) and timed from a voltage level of (VIL + VIH) / 2, SDO loaded with 20 pF, and TA = –40°C to +125°C (unless otherwise noted) MIN NOM MAX UNIT fSCLK SCLK frequency 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 10 MHz 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 20 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 15 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 30 tSCLKHIG H SCLK high time 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 50 ns 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 25 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 33 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 16 tSCLKLO W SCLK low time 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 50 ns 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 25 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 33 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 16 tSDIS SDI setup, 1.7 V ≤ IOVDD < 2.7 V 13 ns SDI setup, 2.7 V ≤ IOVDD ≤ 5.5 V 8 tSDIH SDI hold, 1.7 V ≤ IOVDD < 2.7 V 13 ns SDI hold, 2.7 V ≤ IOVDD ≤ 5.5 V 8 tCSS SYNC falling edge to SCLK falling edge, 1.7 V ≤ IOVDD < 2.7 V 30 ns SYNC falling edge to SCLK falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tCSH SCLK falling edge to SYNC rising edge, 1.7 V ≤ IOVDD < 2.7 V 15 ns SCLK falling edge to SYNC rising edge, 2.7 V ≤ IOVDD ≤ 5.5 V 10 tCSHIGH SYNC high time, 1.7 V ≤ IOVDD < 2.7 V 55 ns SYNC high time, 2.7 V ≤ IOVDD ≤ 5.5 V 50 tCSIGNO RE SCLK falling edge to SYNC ignore, 1.7 V ≤ IOVDD < 2.7 V 10 ns SCLK falling edge to SYNC ignore, 2.7 V ≤ IOVDD ≤ 5.5 V 5 tLDACSL Synchronous update: SYNC rising edge to LDAC falling edge, 1.7 V ≤ IOVDD < 2.7 V 50 ns Synchronous update: SYNC rising edge to LDAC falling edge, 2.7 V ≤ IOVDD ≤ 5.5 V 50 tLDACW LDAC low time, 1.7 V ≤ IOVDD < 2.7 V 20 ns LDAC low time, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tCLRW CLR low time, 1.7 V ≤ IOVDD < 2.7 V 20 ns CLR low time, 2.7 V ≤ IOVDD ≤ 5.5 V 20 tSDODLY SCLK rising edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 0 0 35 ns SCLK rising edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 0 0 25 SCLK falling edge to SDO valid data, 1.7 V ≤ IOVDD < 2.7 V, FSDO = 1 0 35 SCLK falling edge to SDO valid data, 2.7 V ≤ IOVDD ≤ 5.5 V, FSDO = 1 0 25 tSDOZ SYNC rising edge to SDO HiZ, 1.7 V ≤ IOVDD < 2.7 V 0 20 ns SYNC rising edge to SDO HiZ, 2.7 V ≤ IOVDD ≤ 5.5 V 0 20 |
类似零件编号 - DAC11001A_V01 |
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类似说明 - DAC11001A_V01 |
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