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ADE7763ARSRL 数据表(PDF) 9 Page - Analog Devices |
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ADE7763ARSRL 数据表(HTML) 9 Page - Analog Devices |
9 / 56 page ADE7763 Rev. A | Page 9 of 56 Pin No. Mnemonic Description 15 CLKIN Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7763. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for load capacitance requirements. 16 CLKOUT A crystal can be connected across this pin and CLKIN, as described for Pin 15, to provide a clock source for the ADE7763. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. 17 CS Chip Select. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7763 to share the serial bus with several other devices—see the Serial Interface section. 18 SCLK Serial Clock Input for the Synchronous Serial Interface. All serial data transfers are synchronized to this clock—see the Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, such as an opto-isolator output. 19 DOUT Data Output for the Serial Interface. Data is shifted out at this pin upon the rising edge of SCLK. This logic output is normally in a high impedance state, unless it is driving data onto the serial data bus—see the Serial Interface section. 20 DIN Data Input for the Serial Interface. Data is shifted in at this pin upon the falling edge of SCLK—see the Serial Interface section. |
类似零件编号 - ADE7763ARSRL |
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类似说明 - ADE7763ARSRL |
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