MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3–1

REV 2

5/95

1:4 Clock Distribution Chip

The MC10EL/100EL15 is a low skew 1:4 clock distribution chip

designed explicitly for low skew clock distribution applications. The

device can be driven by either a differential or single-ended ECL or, if

positive power supplies are used, PECL input signal. If a single-ended

input is to be used the VBB output should be connected to the CLK input

and bypassed to ground via a 0.01

µF capacitor. The VBB output is

designed to act as the switching reference for the input of the EL15 under

single-ended input conditions, as a result this pin can only source/sink up

to 0.5mA of current.

The EL15 features a multiplexed clock input to allow for the distribution

of a lower speed scan or test clock along with the high speed system

clock. When LOW (or left open and pulled LOW by the input pulldown

resistor) the SEL pin will select the differential clock input.

The common enable (EN) is synchronous so that the outputs will only

be enabled/disabled when they are already in the LOW state. This avoids

any chance of generating a runt clock pulse when the device is

enabled/disabled as can happen with an asynchronous control. The

internal flip flop is clocked on the falling edge of the input clock, therefore

all associated specification limits are referenced to the negative edge of

the clock input.

LOGIC DIAGRAM AND PINOUT ASSIGNMENT

Q0

Q1

Q2

Q3

15

16

14

13

12

11

10

2

1

34567

VCC

9

8

Q3

Q2

Q1

Q0

EN

SCLK

CLK

CLK

VBB

SEL

VEE

D

Q

1

0

MC10EL15

MC100EL15

D SUFFIX

PLASTIC SOIC PACKAGE

CASE 751B-05

1

16

PIN

FUNCTION

CLK

Diff Clock Inputs

SCLK

Scan Clock Input

EN

Sync Enable

SEL

Clock Select Input

VBB

Reference Output

Q0–3

Diff Clock Outputs

PIN DESCRIPTION

CLK

L

H

X

X

X

SCLK

X

X

L

H

X

SEL

L

L

H

H

X

EN

L

L

L

L

H

Q

L

H

L

H

L*

FUNCTION TABLE

* On next negative transition of

CLK or SCLK