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CAT24WC164RA-TE13 数据表(PDF) 4 Page - Catalyst Semiconductor

部件名 CAT24WC164RA-TE13
功能描述  16K-Bit Serial EEPROM, Cascadable
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制造商  CATALYST [Catalyst Semiconductor]
网页  http://www.catalyst-semiconductor.com
标志 CATALYST - Catalyst Semiconductor

CAT24WC164RA-TE13 数据表(HTML) 4 Page - Catalyst Semiconductor

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CAT24WC164
4
Doc. No. 1026, Rev. I
FUNCTIONAL DESCRIPTION
The CAT24WC164 supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. Data transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC164
operates as a Slave device. Both the Master and Slave
devices can operate as either transmitter or receiver, but
the Master device controls which mode is activated. A
maximum of 8 devices may be connected to the bus as
determined by the device address inputs A0, A1, and A2.
PIN DESCRIPTIONS
SCL:
Serial Clock
The CAT24WC164 serial clock input pin is used to clock
all data transfers into or out of the device. This is an input
pin.
SDA:
Serial Data/Address
The CAT24WC164 bidirectional serial data/address pin
is used to transfer data into and out of the device. The
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
A0, A1, A2:
Device Address Inputs
These inputs set device address when cascading multiple
devices. When these pins are left floating the default
values are zeros.
A maximum of eight devices can be cascaded. If only
one CAT24WC164 is addressed on the bus, all three
Figure 2. Write Cycle Timing
Figure 1. Bus Timing
Figure 3. Start/Stop Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK
8TH BIT
BYTE n
SCL
SDA
START BIT
SDA
STOP BIT
SCL


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