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LP8733 Datasheet(数据表) 13 Page - Texas Instruments

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部件型号  LP8733
说明  LP8733xx Dual High-Current Buck Converter and Dual Linear Regulator
下载  82 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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LP8733 Datasheet(HTML) 13 Page - Texas Instruments

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 13 page
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SCL
SDA
tLOW
trCL
tHD;DAT
tHIGH
tfCL
tSU;DAT
tSU;STA
tSU;STO
START
REPEATED
START
STOP
tHD;STA
START
tSP
trDA
tBUF
tfDA
tHD;STA
S
RS
P
S
13
LP8733
www.ti.com
SNVSBK2 – SEPTEMBER 2019
Product Folder Links: LP8733
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
I
2C Serial Bus Timing Parameters (continued)
These specifications are ensured by design. Unless otherwise noted, VIN_Bx = 3.7 V. See
(1) and Figure 1.
MIN
MAX
UNIT
tfDA
Fall time of SDA signal
Standard mode
300
ns
Fast mode
20 × (VDD / 5.5
V)
300
Fast mode+
20 × (VDD / 5.5
V)
120
High-speed mode, Cb = 100 pF
10
80
High-speed mode, Cb = 400 pF
30
160
trCL
Rise time of SCL signal
Standard mode
1000
ns
Fast mode
20
300
Fast mode+
120
High-speed mode, Cb = 100 pF
10
40
High-speed mode, Cb = 400 pF
20
80
trCL1
Rise time of SCL signal
after a repeated start
condition and after an
acknowledge bit
High-speed mode, Cb = 100 pF
10
80
ns
High-speed mode, Cb = 400 pF
20
160
tfCL
Fall time of a SCL signal
Standard mode
300
ns
Fast mode
20 × (VDD / 5.5
V)
300
Fast mode+
20 × (VDD / 5.5
V)
120
High-speed mode, Cb = 10 – 100 pF
10
40
High-speed mode, Cb = 400 pF
20
80
Cb
Capacitive load for each
bus line (SCL and SDA)
400
pF
tSP
Pulse width of spike
suppressed (SCL and
SDA spikes that are less
then the indicated width
are suppressed)
Standard mode, fast mode, and fast mode+
50
ns
High-speed mode
10
Figure 1. I2C Timing




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