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LP8733 Datasheet(数据表) 77 Page - Texas Instruments

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部件型号  LP8733
说明  LP8733xx Dual High-Current Buck Converter and Dual Linear Regulator
下载  82 Pages
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
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LP8733 Datasheet(HTML) 77 Page - Texas Instruments

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 77 page
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LP8733
www.ti.com
SNVSBK2 – SEPTEMBER 2019
Product Folder Links: LP8733
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Copyright © 2019, Texas Instruments Incorporated
Layout Guidelines (continued)
4. If remote voltage sensing can be used for the load, connect the LP8733xx feedback pins FB_Bx to the
respective sense pins on the load capacitor. The sense lines are susceptible to noise. They must be kept
away from noisy signals such as PGND_Bx, VIN_Bx, and SW_Bx, as well as high bandwidth signals such as
the I2C. Avoid both capacitive and inductive coupling by keeping the sense lines short and direct, and close
to each other. Run the lines in a quiet layer. Isolate them from noisy signals by a voltage or ground plane if
possible. If series resistors are used for load current measurement, place them after connection of the
voltage feedback.
5. PGND_Bx, VIN_Bx and SW_Bx must be routed on thick layers. They must not surround inner signal layers
which are not able to withstand interference from noisy PGND_Bx, VIN_Bx and SW_Bx.
6. LDO performance (PSRR, noise, and transient response) depend on the layout of the PCB. Best
performance is achieved by placing CIN and COUT as close to the LP8733xx device as practical. The
ground connections for CIN and COUT must be back to the LP8733xx AGND with as wide and as short of a
copper trace as is practical and with multiple vias if routing is done on other layer. Avoid connections using
long trace lengths, narrow trace widths, or connection through small via. These add parasitic inductances
and resistance that results in inferior performance, especially during transient conditions.
Due to the small package of this converter and the overall small solution size, the thermal performance of the
PCB layout is important. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and
convection surfaces, and the presence of other heat-generating components affect the power dissipation limits of
a given component. Proper PCB layout, focusing on thermal performance, results in lower die temperatures.
Wide power traces can sink dissipated heat. This can be improved further on multi-layer PCB designs with vias
to different planes. This results in reduced junction-to-ambient (RθJA) and junction-to-board (RθJB) thermal
resistances, thereby reducing the device junction temperature, TJ. TI strongly recommends performance of a
careful system-level 2D or full 3D dynamic thermal analysis at the beginning product design process by using a
thermal modeling analysis software.




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