数据搜索系统,热门电子元器件搜索
  Chinese▼

Delete All
ON OFF
ALLDATASHEETCN.COM

X  

预览 PDF Download HTML

865G Datasheet(数据表) 5 Page - Intel Corporation

部件型号  865G
说明  Intel 865G/865GV Graphics and Memory Controller Hub
下载  249 Pages
Scroll/Zoom Zoom In 100% Zoom Out
制造商  INTEL [Intel Corporation]
网页  http://www.intel.com
标志 

865G Datasheet(HTML) 5 Page - Intel Corporation

 
Zoom Inzoom in Zoom Outzoom out
 5 page
background image
6
Intel® 82865G/82865GV GMCH Datasheet
3.8
PCI-to-CSA Bridge Registers (Device 3) ..................................................... 113
3.8.1
VID3—Vendor Identification Register (Device 3)............................ 114
3.8.2
DID3—Device Identification Register (Device 3) ............................ 114
3.8.3
PCICMD3—PCI Command Register (Device 3)............................. 115
3.8.4
PCISTS3—PCI Status Register (Device 3) .................................... 116
3.8.5
RID3—Revision Identification Register (Device 3) ......................... 117
3.8.6
SUBC3—Class Code Register (Device 3) ...................................... 117
3.8.7
BCC3—Base Class Code Register (Device 3) ............................... 117
3.8.8
MLT3—Master Latency Timer Register (Device 3)......................... 118
3.8.9
HDR3—Header Type Register (Device 3) ...................................... 118
3.8.10 PBUSN3—Primary Bus Number Register (Device 3)..................... 118
3.8.11 SBUSN3—Secondary Bus Number Register (Device 3) ................ 119
3.8.12 SMLT3—Secondary Bus Master Latency Timer Register
(Device 3) ....................................................................................... 119
3.8.13 IOBASE3—I/O Base Address Register (Device 3) ......................... 120
3.8.14 IOLIMIT3—I/O Limit Address Register (Device 3) .......................... 120
3.8.15 SSTS3—Secondary Status Register (Device 3)............................. 121
3.8.16 MBASE3—Memory Base Address Register (Device 3).................. 122
3.8.17 MLIMIT3—Memory Limit Address Register (Device 3)................... 123
3.8.18 PMBASE3—Prefetchable Memory Base Address Register
(Device 3) ....................................................................................... 124
3.8.19 PMLIMIT3—Prefetchable Memory Limit Address Register
(Device 3) ....................................................................................... 124
3.8.20 BCTRL3—Bridge Control Register (Device 3)................................ 125
3.8.21 ERRCMD3—Error Command Register (Device 3) ......................... 126
3.8.22 CSACNTRL—CSA Control Register (Device 3) ............................. 126
3.9
Overflow Configuration Registers (Device 6)............................................... 127
3.9.1
VID6—Vendor Identification Register (Device 6)............................ 127
3.9.2
DID6—Device Identification Register (Device 6) ............................ 128
3.9.3
PCICMD6—PCI Command Register (Device 6)............................. 128
3.9.4
PCISTS6—PCI Status Register (Device 6) .................................... 129
3.9.5
RID6—Revision Identification Register (Device 6) ......................... 129
3.9.6
SUBC6—Sub-Class Code Register (Device 6) .............................. 130
3.9.7
BCC6—Base Class Code Register (Device 6) ............................... 130
3.9.8
HDR6—Header Type Register (Device 6) ...................................... 130
3.9.9
BAR6—Memory Delays Base Address Register (Device 6)........... 131
3.9.10 SVID6—Subsystem Vendor Identification Register
(Device 6) ....................................................................................... 131
3.9.11 SID6—Subsystem Identification Register (Device 6)...................... 131
3.10
Device 6 Memory-Mapped I/O Register Space ........................................... 132
3.10.1 DRB[0:7]—DRAM Row Boundary Register
(Device 6, MMR) ............................................................................. 132
3.10.2 DRA—DRAM Row Attribute Register (Device 6, MMR) ................. 134
3.10.3 DRT—DRAM Timing Register (Device 6, MMR) ............................ 135
3.10.4 DRC—DRAM Controller Mode Register (Device 6, MMR) ............. 136
4
System Address Map ......................................................................................139
4.1
System Memory Address Ranges ............................................................... 139
4.2
Compatibility Area........................................................................................ 141
4.3
Extended Memory Area ............................................................................... 143
4.3.1
15 MB–16 MB Window ................................................................... 143
4.3.2
Pre-Allocated Memory .................................................................... 144




HTML 页

1  2  3  4  5  6  7  8  9  10  11  12  13  14  15  16  17  18  19  20  21  22  23  24  25  26  27  28  29  30  31  32  33  34  35  36  37  38  39  40  41  42  43  44  45  46  47  48  49  50  51  52  53  54  55  56  57  58  59  60  61  62  63  64  65  66  67  68  69  70  71  72  73  74  75  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90  91  92  93  94  95  96  97  98  99  100   ...More


数据表 下载




链接网址


Privacy Policy
ALLDATASHEETCN.COM
ALLDATASHEET是否为您带来帮助?  [ DONATE ]  

关于 Alldatasheet    |   广告服务   |   联系我们   |   隐私政策   |   书签   |   链接交换   |   制造商名单
All Rights Reserved© Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  , Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp  |   Russian : Alldatasheetru.com
Korean : Alldatasheet.co.kr   |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com  |   Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl