865G Datasheet(数据表) 2 Page

2 page

Intel® 82865G/82865GV GMCH Datasheet

Contents

Introduction...........................................................................................................15

1.1

Terminology ...................................................................................................16

1.2

Related Documents .......................................................................................17

1.3

Intel® 865G Chipset System Overview ..........................................................18

1.4

Intel® 82865G GMCH Overview ....................................................................20

1.4.1

Host Interface....................................................................................20

1.4.2

System Memory Interface .................................................................20

1.4.3

Hub Interface ....................................................................................21

1.4.4

Communications Streaming Architecture (CSA) Interface................21

1.4.5

Multiplexed AGP and Intel® DVO Interface.......................................21

1.4.6

Graphics Overview............................................................................22

1.4.7

Display Interface ...............................................................................24

1.5

Clock Ratios...................................................................................................24

Signal Description ..............................................................................................25

2.1

Host Interface Signals....................................................................................27

2.2

Memory Interface ...........................................................................................30

2.2.1

DDR SDRAM Channel A ..................................................................30

2.2.2

DDR SDRAM Channel B ..................................................................31

2.3

Hub Interface .................................................................................................32

2.4

Communication Streaming Architecture (CSA) Interface...............................32

2.5

AGP Interface ................................................................................................33

2.5.1

AGP Addressing Signals...................................................................33

2.5.2

AGP Flow Control Signals ................................................................34

2.5.3

AGP Status Signals ..........................................................................34

2.5.4

AGP Strobes .....................................................................................35

2.5.5

PCI Signals–AGP Semantics............................................................36

2.5.5.1

PCI Pins during PCI Transactions on AGP Interface ........37

2.5.6

Multiplexed Intel® DVOs on AGP ......................................................37

2.5.7

Intel® DVO-to-AGP Pin Mapping.......................................................39

2.6

Analog Display Interface ................................................................................40

2.7

Clocks, Reset, and Miscellaneous Signals ....................................................41

2.8

RCOMP, VREF, VSWING Signals.................................................................42

2.9

Power and Ground Signals ............................................................................43

2.10

GMCH Sequencing Requirements.................................................................44

2.11

Signals Used As Straps .................................................................................45

2.11.1 Functional Straps ..............................................................................45

2.11.2 Strap Input Signals............................................................................45

2.12

Full and Warm Reset States ..........................................................................46

3.1

3.2

Platform Configuration Structure....................................................................48

3.3

Routing Configuration Accesses....................................................................50

3.3.1

Standard PCI Bus Configuration Mechanism ...................................50

3.3.2

PCI Bus #0 Configuration Mechanism ..............................................50

3.3.3

Primary PCI and Downstream Configuration Mechanism.................50

3.3.4

AGP/PCI_B Bus Configuration Mechanism ......................................51

865G Datasheet(数据表) 2 Page - Intel Corporation

865G Datasheet(HTML) 2 Page - Intel Corporation

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