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CS18LV02565ABI-70 Datasheet(数据表) 4 Page - List of Unclassifed Manufacturers

部件型号  CS18LV02565ABI-70
说明  HIGH SPEED SUPER LOW POWER SRAM
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制造商  ETC1 [List of Unclassifed Manufacturers]
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CS18LV02565ABI-70 Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers

 
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High Speed Super Low Power SRAM
32K-Word By 8 Bit
CS18LV02565
4
Rev. 2.0
Chiplus reserves the right to change product or specification without notice.
PIN DESCRIPTIONS
Name
Type
Function
A0 – A14
Input
Address inputs for selecting one of the 32,768 x 8 bit words in the RAM
/CE
Input
/CE is active LOW. Chip enable must be active when data read from or write
to the device. If chip enable is not active, the device is deselected and in a
standby power mode. The DQ pins will be in high impedance state when the
device is deselected.
/WE
Input
The Write enable input is active LOW. It controls read and write operations.
With the chip selected, when /WE is HIGH and /OE is LOW, output data will
be present on the DQ pins, when /WE is LOW, the data present on the DQ
pins will be written into the selected memory location.
/OE
Input
The output enable input is active LOW. If the output enable is active while the
chip is selected and the write enable is inactive, data will be present on the
DQ pins and they will be enabled. The DQ pins will be in the high impedance
state when /OE is inactive.
DQ0~DQ7
I/O
These 8 bi-directional ports are used to read data from or write data into the
RAM.
Vcc
Power
Power Supply
Gnd
Power
Ground
TRUTH TABLE
Mode
/CE
/WE
/OE
DQ0~7
Vcc Current
Standby
H
X
X
High Z
ICCSB, ICCSB1
Output Disabled
L
H
H
High Z
ICC
Read
L
H
L
DOUT
ICC
Write
L
L
X
DIN
ICC




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