数据搜索系统,热门电子元器件搜索 |
|
GS4982-CKAE3 数据表(PDF) 5 Page - Gennum Corporation |
|
GS4982-CKAE3 数据表(HTML) 5 Page - Gennum Corporation |
5 / 7 page 5 of 7 521 - 61 - 01 ODD / EVEN OUTPUT (Pin 7) VCC (Pin 8) RSET (Pin 6) VERTICAL SYNC OUTPUT (PIN 3) BACK PORCH DETECTOR COMPOSITE SYNC OUTPUT (Pin 1) HORIZONTAL CLEN VERTICAL DETECTOR INTEGRATED HOLD FILTER BESSEL 2ND ORDER SIGNAL DETECT MUTE WINDOWING CIRCUIT FAULT HANDLING CLAMP WINDOW + + - - BACK PORCH OUTPUT (Pin 5) VOLTAGE REGULATOR TIMING CURRENTS - + CLK Q D Q G Q Q D CLK D Q Q 227k 0.1 µ VHC VSC VSC + - R 50% POINT R INTEGRATED HOLD 2ND ORDER BESSEL FILTER FAULT HANDLING CLAMP WINDOW VIDEO INPUT (Pin 2) NO SYNC BPEN 0.1 µ Assuming that the sync separator is in steady state operation with a valid input signal, all outputs will be enabled. Removal of the input signal, or a significant change in the input signal frequency, will cause an internal probation timer to be triggered. While on probation, the sync separator outputs remain enabled and separated sync is still produced. If a valid input signal is not returned to the system before the probation time expires (typically 2.5 ms), all outputs will be muted to logic high state. Should a valid signal return during the probation period, and eight lines be received before the probation time expires, device outputs will remain enabled. Once device outputs are muted, the device must receive 8 valid lines of video at the correct horizontal frequency before the outputs are re-enabled. SIGNAL DETECT AND OUTPUT MUTE Internal to the GS4882 and GS4982 is a robust video signal detection circuit. This circuit provides a reliable control signal that will enable the sync separator outputs only when a valid video signal is present. When the input signal is not valid, the outputs are muted and stay in a logic high state. The GS4882 and GS4982 differentiate between valid and in- valid input signals by feeding the horizontal sync information into a frequency to voltage converter. The horizontal scan rate of the input signal is then compared to an expected input signal horizontal scan rate. With R SET =227 k Ω, the sync separator will typically define a valid input signal as one with a horizontal frequency of 15.7 ± 4 kHz. Fig. 6 GS4882 Block Diagram ODD / EVEN OUTPUT (Pin 7) VCC (Pin 8) RSET (Pin 6) VERTICAL SYNC OUTPUT (PIN 3) BACK PORCH DETECTOR HORIZONTAL (Pin 1) HORIZONTAL VERTICAL DETECTOR SIGNAL DETECT MUTE + + - - BACK PORCH OUTPUT (Pin 5) VOLTAGE REGULATOR TIMING CURRENTS - - + + CLK Q D Q G Q Q D CLK D Q Q 227k 0.1 µ R 50% POINT R 2ND ORDER BESSEL FILTER VIDEO INPUT (Pin 2) NO SYNC 0.1 µ WINDOWING CIRCUIT CLAMP WINDOW INTEGRATED HOLD FAULT HANDLING VSC VHC VSC CLEN BPEN Fig. 7 GS4982 Block Diagram |
类似零件编号 - GS4982-CKAE3 |
|
类似说明 - GS4982-CKAE3 |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |