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LXT974 数据表(PDF) 39 Page - Intel Corporation |
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LXT974 数据表(HTML) 39 Page - Intel Corporation |
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39 / 74 page  Fast Ethernet 10/100 Quad Transceivers — LXT974/LXT975 Datasheet 39 2.8 Operating Requirements 2.8.1 Power Requirements The LXT974/975 requires four +5V supply inputs (VCC, VCCR, VCCT, and VCCH). These inputs may be supplied from a single source although decoupling is required to each respective ground. As a matter of good practice, these supplies should be as clean as possible. Typical filtering and decoupling are shown in Figure 22 on page 46. 2.8.1.1 MII Power Requirements An additional supply may be used for the MII (VCCMII). The supply may be either +5V or +3.3V. When the MII supply is 3.3V, MII inputs may not be driven with 5V levels. VCCMII should be supplied from the same power source used to supply the controller on the other side of the MII interface. Refer to Table 25 on page 51 for MII I/O characteristics. 2.8.1.2 Low-Voltage Fault Detect The LXT974/975 has a low-voltage fault detection function that prevents transmission of invalid symbols when VCC goes below normal operating levels. This function disables the transmit outputs when a low- voltage fault on VCC occurs. If this condition happens, bit 20.2 is set High. Operation is automatically restored when VCC returns to normal. Table 27 on page 51 indicates voltage levels used to detect and clear the low-voltage fault condition. 2.8.1.3 Power Down Mode The LXT974/975 goes into Power Down Mode when PWRDWN is asserted. In this mode, all functions are disabled except the MDIO. The power supply current is significantly reduced. This mode can be used for energy-efficient applications or for redundant applications where there are two devices and one is left as a standby. When the LXT974/975 is returned to normal operation, configuration settings of the MDIO registers are maintained. Refer to Table 23 on page 50 for power down specifications. 2.8.2 Clock Requirements The LXT974/975 requires a constant 25 MHz clock (CLK25M) that must be enabled at all times. Refer to Test Specifications, Table 26 on page 51, for clock timing requirements. Table 20. LED-DAT Serial Port Bit Assignments Port 0 Port 1 Port 2 Port 3 231 22 21 20 19 18 17 16 15 14 13 12 11 : 6 5 4 3 2 1 0 T R L D S C T R L D S C T R L D S C T R L D S C 1. Bit 23 is shifted out first. |
类似零件编号 - LXT974 |
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类似说明 - LXT974 |
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