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CX20493 Datasheet(数据表) 90 Page - Conexant Systems, Inc

部件型号  CX20493
说明  SmartV.XX Modem
下载  94 Pages
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制造商  CONEXANT [Conexant Systems, Inc]
网页  http://www.conexant.com
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CX20493 Datasheet(HTML) 90 Page - Conexant Systems, Inc

 
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CX81801-7x/8x SmartV.XX Modem Data Sheet
5-10
Conexant
102199B
5.2.10
Divisor Registers (Addr = 0 and 1, DLAB = 1)
The Divisor Latch LS (least significant byte) and Divisor Latch MS (most significant
byte) are two read-write registers at locations 0 and 1 when DLAB = 1, respectively.
The baud rate is selected by loading each divisor latch with the appropriate hex value.
Programmable values corresponding to the desired baud rate are listed in Table 5-3.
1.
SCR - Scratch Register (Addr = 7)
The Scratchpad Register is a read-write register at location 7. This register is not used by
the modem and can be used by the host for temporary storage.
Table 5-3. Programmable Baud Rates
Divisor Latch (Hex)
MS
LS
Divisor (Decimal)
Baud Rate
06
00
1536
75
04
17
1047
110
03
00
768
150
01
80
384
300
00
C0
192
600
00
60
96
1200
00
30
48
2400
00
18
24
4800
00
0C
12
9600
00
06
6
19200
00
04
4
28800
00
03
3
38400
00
02
2
57600
00
01
1
115200
00
00
NA
230400
5.3
Receiver FIFO Interrupt Operation
5.3.1
Receiver Data Available Interrupt
When the FIFO mode is enabled (FCR0 = 1) and receiver interrupt (RX Data Available)
is enabled (IER0 = 1), receiver interrupt operation is as follows:
The Receiver Data Available Flag (LSR0) is set as soon as a received data character is
available in the RX FIFO. LSR0 is cleared when the RX FIFO is empty.
The Receiver Data Available interrupt code (IIR0-IIR4 = 4h) is set whenever the number
of received data bytes in the RX FIFO reaches the trigger level specified by FCR6-FCR7
bits; it is cleared whenever the number of received data bytes in the RX FIFO drops
below the trigger level specified by FCR6-FCR7 bits.
The HINT interrupt is asserted whenever the number of received data bytes in the RX
FIFO reaches the trigger level specified by FCR6-FCR7 bits. HINT interrupt is de-
asserted when the number of received data bytes in the RX FIFO drops below the trigger
level specified by FCR6-FCR7 bits.




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