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CX20493 Datasheet(数据表) 87 Page - Conexant Systems, Inc

部件型号  CX20493
说明  SmartV.XX Modem
下载  94 Pages
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制造商  CONEXANT [Conexant Systems, Inc]
网页  http://www.conexant.com
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CX20493 Datasheet(HTML) 87 Page - Conexant Systems, Inc

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CX81801-7x/8x SmartV.XX Modem Data Sheet
102199B
Conexant
5-7
5.2.5
MCR - Modem Control Register (Addr = 4)
The Modem Control Register (MCR) controls the interface with the modem or data set.
Bit 7-5
Not used.
Always 0.
Bit 4
Local Loopback.
When this bit is set to a 1, the diagnostic mode is selected and the following occurs:
Data written to the Transmit Buffer is looped back to the Receiver Buffer.
The DTS (MCR0), RTS (MCR1), Out1 (MCR2), and Out2 (MCR3) modem control
register bits are internally connected to the DSR (MSR5), CTS (MSR4), RI (MSR6), and
DCD (MSR7) modem status register bits, respectively.
Bit 3
Output 2.
When this bit is a 1, HINT is enabled. When this bit is a 0, HINT is in the high
impedance state.
Bit 2
Output 1.
This bit is used in local loopback (see MCR4).
Bit 1
Request to Send (RTS).
This bit controls the Request to Send (RTS) function. When this bit is a 1, RTS is on.
When this bit is a 0, RTS is off.
Bit 0
Data Terminal Ready (DTR).
This bit controls the Data Terminal Ready (DTR) function. When this bit is a 1, DTR is
on. When this bit is a 0, DTR is off.
5.2.6
LSR - Line Status Register (Addr = 5)
This 8-bit register provides status information to the host concerning data transfer.
Bit 7
RX FIFO Error.
In the 16450 mode, this bit is not used and is always 0.
In the FIFO mode, this bit is set if there are one or more characters in the RX FIFO
with a parity error, framing error, or break indication detected. This bit is reset to a 0
when the host reads the LSR and none of the above conditions exist in the RX FIFO.
Bit 6
Transmitter Empty (TEMT).
This bit is set to a 1 whenever the TX Buffer (THR) and equivalent of the Transmitter
Shift Register (TSR) are both empty. It is reset to a 0 whenever either the THR or the
equivalent of the TSR contains a character.
In the FIFO mode, this bit is set to a 1 when ever the TX FIFO and the equivalent of
the TSR are both empty.




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