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CX20493 数据表(PDF) 40 Page - Synaptics Incorporated. |
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CX20493 数据表(HTML) 40 Page - Synaptics Incorporated. |
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40 / 94 page  CX81801-7x/8x SmartV.XX Modem Data Sheet 3-8 Conexant 102199B Table 3-2. CX81801 Modem Pin Signal Definitions for Parallel Interface (PARIF = High) Label Pin I/O I/O Type Signal Name/Description System XTLI, XTLO 114, 115 I, O Ix, Ox Crystal In and Crystal Out. If an external 28.224 MHz crystal circuit is used instead of an external clock circuit, connect XTLI and XTLO to the external crystal circuit and connect CLKIN to digital ground (GND). CLKIN 113 I It Clock In. If an external 28.224 MHz clock circuit is used instead of an external crystal circuit, connect CLKIN to the clock output and leave XTLI and XTLO open. CLKOUT 61 O It/Ot2 Clock Out. 28.224 MHz output clock. Leave open. DV1TP 111 I Itpu Clock Input Select. This input is used to choose the clock input. Connect to +3.3V or leave open to select XTLI as the clock input. Connect to GND to select CLKIN as the clock input. PARIF 5 I Itpu Parallel/Serial Interface Select. PARIF input high (open) selects parallel host interface operation (see this table); PARIF low (GND) selects serial DTE interface operation (see Table 3-4). LINE_SEL (PE7) 23 I It/Ot8 Line Interface Select. Selects telephone line interface. Connect to +3.3V though 47 K Ω. STPMODE# (PD3) 9 I Ith/Ot2 Stop Mode. Not used. Leave open. NMI# 117 I Ithpu Non-Maskable Interrupt. Not used. Connect to +3.3V. RESET# 34 I It Reset. The active low RESET# input resets the Smart Modem logic, and restores the saved configuration from serial EEPROM or returns the modem to the factory default values if NVRAM is not present. RESET# low holds the modem in the reset state; RESET# going high releases the modem from the reset state. After application of VDD, RESET# must be held low for at least 15 ms after the VDD power reaches operating range. The modem device set is ready to use 25 ms after the low-to-high transition of RESET#. For parallel Interface, connect RESET# input to the host bus RESET line through an inverter. VGG 60 P PWRG I/O Signaling Voltage Source. Connect to +3.3V for +3.3V inputs, or to +5V for +5V inputs. VDD 2, 15, 40, 58, 78, 100, 108, 116, 124 P PWR Digital Supply Voltage. Connect to VCC (+3.3V, filtered). VDD_CORE 20, 53, 85 P PWR Core Voltage. Internal core voltage. GND 10, 25, 30, 44, 48, 68, 90, 95, 103, 112, 120, 128 G GND Digital Ground. Connect to digital ground (GND). LPO 57 I I/O Low Power Oscillator. Connect to +3.3V through 240 K Ω. NOXYCK 47 I Itpu Disable XCLK Output. When low, disables XCLK output (reduces internal power consumption). When high, enables XCLK output. Connect to GND. PLLVDD 82 P PWR PLL Circuit Digital Supply Voltage. Connect to +3.3V and to GND through 0.1 µF. PLLGND 83 G GND PLL Circuit Digital Ground. Connect to GND. Serial EEPROM (NVRAM) Interface NVMCLK (PA7) 33 O It/Ot2 NVRAM Clock. NVMCLK output high enables the EEPROM. Connect to EEPROM SCL pin. NVMDATA (PE3) 18 I/O It/Ot2 NVRAM Data. The NVMDATA pin supplies a serial data interface to the EEPROM. Connect to EEPROM SDA pin and to +3.3V through 10 K Ω. |
类似零件编号 - CX20493 |
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类似说明 - CX20493 |
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