数据搜索系统,热门电子元器件搜索 |
|
GD25Q256D 数据表(PDF) 47 Page - GigaDevice Semiconductor (Beijing) Inc. |
|
GD25Q256D 数据表(HTML) 47 Page - GigaDevice Semiconductor (Beijing) Inc. |
47 / 89 page 3.3V Uniform Sector Dual and Quad Serial Flash GD25Q256D 47 7.19. 64KB Block Erase (BE64 D8H or 4BE64 DCH) The 64KB Block Erase (BE) command is erased the all data of the chosen block. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL) bit. The 64KB Block Erase (BE) command is entered by driving CS# low, followed by the command code, and three address Bytes on SI. Any address inside the block is a valid address for the 64KB Block Erase (BE) command. CS# must be driven low for the entire duration of the sequence. The 64KB Block Erase command sequence: CS# goes low sending 64KB Block Erase command 3-Byte address on SI CS# goes high. CS# must be driven high after the eighth bit of the last address Byte has been latched in; otherwise the 64KB Block Erase (BE) command is not executed. As soon as CS# is driven high, the self-timed Block Erase cycle (whose duration is tBE) is initiated. While the Block Erase cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Block Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. A 64KB Block Erase (BE) command applied to a block which is protected by the Block Protect (TB, BP3, BP2, BP1, and BP0) bits is not executed. Figure 49. 64KB Block Erase Sequence Diagram (ADS=0) Figure 50.64KB Block Erase Sequence Diagram (ADS=1) Figure 51. 64KB Block Erase with 4-Byte Address Sequence Diagram (ADS=0 or ADS=1) Command 0 1 2 3 4 5 6 7 D8H CS# SCLK SI 8 9 29 30 31 MSB 2 1 0 24 Bits Address 23 22 Command 0 1 2 3 4 5 6 7 D8H CS# SCLK SI 8 9 37 38 39 MSB 2 1 0 32 Bits Address 31 30 Command 0 1 2 3 4 5 6 7 DCH CS# SCLK SI 8 9 37 38 39 MSB 2 1 0 32 Bits Address 31 30 |
类似说明 - GD25Q256D |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |