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GS74116ATP-7IT 数据表(PDF) 6 Page - GSI Technology |
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GS74116ATP-7IT 数据表(HTML) 6 Page - GSI Technology |
6 / 14 page Rev: 1.03 10/2002 6/14 © 2001, Giga Semiconductor, Inc. Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS74116ATP/J/X AC Characteristics * These parameters are sampled and are not 100% tested. Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL Read Cycle Parameter Symbol -7 -8 -10 -12 Unit Min Max Min Max Min Max Min Max Read cycle time tRC 7 — 8 — 10 — 12 — ns Address access time tAA — 7 — 8 — 10 — 12 ns Chip enable access time (CE)tAC — 7 — 8 — 10 — 12 ns Byte enable access time (UB, LB)tAB — 3 — 3.5 —4—5 ns Output enable to output valid (OE)tOE — 3 — 3.5 —4—5 ns Output hold from address change tOH 3 — 3—3—3— ns Chip enable to output in low Z (CE) tLZ* 3 — 3—3—3— ns Output enable to output in low Z (OE) tOLZ* 0 — 0—0—0— ns Byte enable to output in low Z (UB, LB) tBLZ* 0 — 0—0—0— ns Chip disable to output in High Z (CE) tHZ* — 3.5 —4—5—6 ns Output disable to output in High Z (OE) tOHZ* — 3 — 3.5 —4—5 ns Byte disable to output in High Z (UB, LB) tBHZ* — 3 — 3.5 —4—5 ns tAA tOH tRC Address Data Out Previous Data Data valid |
类似零件编号 - GS74116ATP-7IT |
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类似说明 - GS74116ATP-7IT |
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