BC41B143A-ds-003Pc
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© Cambridge Silicon Radio Limited 2005
Page 5 of 94
List of Figures
Figure 3.1
BlueCore4-ROM Plug-n-Go 10 x 10mm LFBGA Package ........................................................... 9
Figure 7.1
BlueCore4-ROM Plug-n-Go Device Diagram ............................................................................. 32
Figure 9.1
BlueCore HCI Stack.................................................................................................................... 36
Figure 9.2
BlueCore RFCOMM Stack.......................................................................................................... 39
Figure 9.3
Virtual Machine ........................................................................................................................... 41
Figure 9.4
HID Stack.................................................................................................................................... 42
Figure 10.1
Circuit for RF_CONNECT ........................................................................................................... 44
Figure 10.2
Circuit RF_IN .............................................................................................................................. 45
Figure 10.3
TCXO Clock Accuracy ................................................................................................................ 46
Figure 10.4
Actual Allowable Clock Presence Delay on XTAL_IN vs. PS Key Setting.................................. 47
Figure 10.5
Crystal Driver Circuit ................................................................................................................... 49
Figure 10.6
Crystal Equivalent Circuit............................................................................................................ 49
Figure 10.7
Crystal Load Capacitance and Series Resistance Limits with Crystal Frequency...................... 53
Figure 10.8
Crystal Driver Transconductance vs. Driver Level Register Setting ........................................... 54
Figure 10.9
Crystal Driver Negative Resistance as a Function of Drive Level Setting .................................. 55
Figure 10.10
Universal Asynchronous Receiver .............................................................................................. 56
Figure 10.11
Break Signal................................................................................................................................ 57
Figure 10.12
UART Bypass Architecture ......................................................................................................... 58
Figure 10.13
USB Connections for Self-Powered Mode.................................................................................. 60
Figure 10.14
USB Connections for Bus-Powered Mode.................................................................................. 61
Figure 10.15
USB_DETACH and USB_WAKE_UP Signal.............................................................................. 62
Figure 10.16
Write Operation........................................................................................................................... 65
Figure 10.17
Read Operation........................................................................................................................... 65
Figure 10.18
BlueCore4-ROM Plug-n-Go as PCM Interface Master ............................................................... 67
Figure 10.19
BlueCore4-ROM Plug-n-Go as PCM Interface Slave ................................................................. 67
Figure 10.20
Long Frame Sync (Shown with 8-bit Companded Sample) ........................................................ 68
Figure 10.21
Short Frame Sync (Shown with 16-bit Sample) .......................................................................... 68
Figure 10.22
Multi-slot Operation with Two Slots and 8-bit Companded Samples .......................................... 69
Figure 10.23
GCI Interface............................................................................................................................... 69
Figure 10.24
16-Bit Slot Length and Sample Formats ..................................................................................... 70
Figure 10.25
PCM Master Timing Long Frame Sync....................................................................................... 72
Figure 10.26
PCM Master Timing Short Frame Sync ...................................................................................... 72
Figure 10.27
PCM Slave Timing Long Frame Sync......................................................................................... 74
Figure 10.28
PCM Slave Timing Short Frame Sync ........................................................................................ 74
Figure 10.29
Example EEPROM Connection .................................................................................................. 79
Figure 10.30
Example TXCO Enable OR Function.......................................................................................... 80
Figure 13.1
Application Circuit for Radio Characteristics Specification ......................................................... 86
Figure 14.1
BlueCore4-ROM Plug-n-Go 96-Ball LFBGA 1.6mm Package Dimensions ................................ 87
List of Tables
Table 10.1
External Clock Specifications...................................................................................................... 46
Table 10.2
PS Key Values for CDMA/3G Phone TCXO Frequencies .......................................................... 48
Table 10.3
Crystal Specification ................................................................................................................... 50
Table 10.4
Possible UART Settings.............................................................................................................. 56
Table 10.5
Standard Baud Rates.................................................................................................................. 57
Table 10.6
USB Interface Component Values .............................................................................................. 60
Table 10.7
Instruction Cycle for an SPI Transaction..................................................................................... 64
Table 10.8
PCM Master Timing .................................................................................................................... 71
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