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ADSP-21262SKBCZ200 数据表(PDF) 5 Page - Analog Devices

部件名 ADSP-21262SKBCZ200
功能描述  SHARC Processor
Download  44 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADSP-21262SKBCZ200 数据表(HTML) 5 Page - Analog Devices

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ADSP-21262
Rev. A
|
Page 5 of 44
|
May 2004
Independent, Parallel Computation Units
Within each processing element is a set of computational units.
The computational units consist of an arithmetic/logic unit
(ALU), multiplier, and shifter. These units perform all opera-
tions in a single cycle. The three units within each processing
element are arranged in parallel, maximizing computational
throughput. Single multifunction instructions execute parallel
ALU and multiplier operations. In SIMD mode, the parallel
ALU and multiplier operations occur in both processing ele-
ments. These computation units support IEEE 32-bit single-
precision floating-point, 40-bit extended precision floating-
point, and 32-bit fixed-point data formats.
Data Register File
A general-purpose data register file is contained in each
processing element. The register files transfer data between the
computation units and the data buses, and store intermediate
results. These 10-port, 32-register (16 primary, 16 secondary)
register files, combined with the ADSP-2126x enhanced Har-
vard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0-R15 and in PEY as S0-S15.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-21262 features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With the ADSP-21262’s separate pro-
gram and data memory buses and on-chip instruction cache,
the processor can simultaneously fetch four operands (two over
each data bus) and one instruction (from the cache), all in a sin-
gle cycle.
Instruction Cache
The ADSP-21262 includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-21262’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Figure 2. ADSP-21262 System Sample Configuration
DAI
SPORT5
SPORT4
SPORT3
SPORT2
SPO RT1
SPORT0
SCLK0
SD0A
SFS0
SD0B
SRU
DAI_P 1
DAI _P2
DAI _P3
DAI_P 18
DAI_P 19
DAI _P 20
DAC
(OPTI ONAL)
ADC
(OPTI ONAL)
FS
CLK
SDAT
FS
CLK
SDAT
3
CLOCK
FLAG3 -1
2
2
CLKIN
XTAL
CLK_CFG1 -0
BOO TCFG 1-0
ADDR
PARALLEL
PORT
RAM , ROM
BOOT ROM
I/O DE VICE
OE
DATA
WE
RD
WR
CLKO UT
ALE
AD15 -0
LATCH
RESE T
JTAG
6
ADSP-212 62
CS
FLAG0
PCGB
PCG A
CLK
FS


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