SN74AUP1G34DCKR-PDSO-G5 datasheet(1/13 Pages) TI

部件名	SN74AUP1G34DCKR-PDSO-G5

功能描述	LOW-POWER SINLE BUFFER GATE

Download	13 Pages

Scroll/Zoom	100%

制造商	TI [Texas Instruments]

网页	http://www.ti.com

标志

1 / 13 page

SN74AUP1G34

LOW POWER SINGLE BUFFER GATE

SCES603B – AUGUST 2004 – REVISED JUNE 2005

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

D Available in the Texas Instruments

NanoStar

 and NanoFree Packages

D Low Static-Power Consumption;

ICC = 0.9 µA Max

D Low Dynamic-Power Consumption;

Cpd = 4.1 pF Typ at 3.3 V

D Low Input Capacitance; Ci = 1.5 pF Typ

D Low Noise − Overshoot and Undershoot

<10% of VCC

D Ioff Supports Partial-Power-Down Mode

Operation

D Input Hysteresis Allows Slow Input

Transition and Better Switching Noise

Immunity at the Input

(Vhys = 250 mV Typ at 3.3 V)

D Wide Operating VCC Range of 0.8 V to 3.6 V

D Optimized for 3.3-V Operation

D 3.6-V I/O Tolerant to Support Mixed-Mode

Signal Operation

D tpd = 3.8 ns Max at 3.3 V

D Suitable for Point-to-Point Applications

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Performance Tested Per JESD 22

− 2000-V Human-Body Model

(A114-B, Class II)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

D ESD Protection Exceeds ±5000 V With

Human-Body Model

3

2

4

5

1

NC

VCC

Y

A

GND

DBV PACKAGE

(TOP VIEW)

YEP OR YZP PACKAGE

(BOTTOM VIEW)

DCK PACKAGE

(TOP VIEW)

3

2

4

5

1

NC

VCC

Y

A

GND

3

2

4

5

1

NC

VCC

Y

A

GND

DNU

GND

VCC

Y

A

DRL PACKAGE

(TOP VIEW)

See mechanical drawings for dimensions.

1

4

2

3

5

DNU – Do not use

description /ordering information

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable

applications. This family ensures a very low static and dynamic power consumption across the entire VCC range

of 0.8 V to 3.6 V resulting in an increased battery life. This product also maintains excellent signal integrity (see

Figures 1 and 2).

Figure 1. AUP − The Lowest-Power Family

AUP

LVC

AUP

LVC

Static-Power Consumption

(

µA)

Dynamic-Power Consumption

(pF)

† Single, dual, and triple gates

3.3-V

Logic†

3.3-V

Logic†

0%

20%

40%

60%

80%

100%

0%

20%

40%

60%

80%

100%

−0.5

0

0.5

1

1.5

2

2.5

3

3.5

05

10

15

20

25

30

35

40

45

Figure 2. Excellent Signal Integrity

Time − ns

† AUP1G08 data at CL = 15 pF

Switching Characteristics

at 25 MHz†

Output

Input

Copyright

 2005, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

NanoStar and NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

类似零件编号 - SN74AUP1G34DCKR-PDSO-G5

制造商	部件名	数据表	功能描述
Texas Instruments	SN74AUP1G34DCKR	1,015Kb / 22P	[Old version datasheet] LOW-POWER SINGLE BUFFER GATE
	SN74AUP1G34DCKR	1Mb / 33P	[Old version datasheet] Low-Power Single Buffer Gate
	SN74AUP1G34DCKRE4	1,015Kb / 22P	[Old version datasheet] LOW-POWER SINGLE BUFFER GATE
	SN74AUP1G34DCKRG4	1,015Kb / 22P	[Old version datasheet] LOW-POWER SINGLE BUFFER GATE

More results

类似说明 - SN74AUP1G34DCKR-PDSO-G5

制造商	部件名	数据表	功能描述
Texas Instruments	SN74AUP1G34	1Mb / 33P	[Old version datasheet] Low-Power Single Buffer Gate
	SN74AUP3G34	282Kb / 12P	[Old version datasheet] LOW-POWER TRIPLE BUFFER GATE
	SN74AUP1G34	1,015Kb / 22P	[Old version datasheet] LOW-POWER SINGLE BUFFER GATE
	SN74AUP2G34	907Kb / 19P	[Old version datasheet] LOW-POWER DUAL BUFFER GATE
	SN74AUP3G34	1Mb / 22P	[Old version datasheet] LOW-POWER TRIPLE BUFFER GATE
Analog Devices	AD822-EP	320Kb / 20P	Sinle-Supply, Rail-to-Rail Low Power FET-Input Op Amp REV. 0
Texas Instruments	SN74AUP1G126	1,023Kb / 26P	[Old version datasheet] LOW-POWER SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT
	SN74AUP2G125	869Kb / 21P	[Old version datasheet] LOW-POWER DUAL BUS BUFFER GATE WITH 3-STATE OTPUTS
	SN74AUP1G125_017	1Mb / 46P	[Old version datasheet] Low-Power Single Bus Buffer Gate With 3-State Output
	SN74AUP1G126_017	1Mb / 43P	[Old version datasheet] Low-Power Single Bus Buffer Gate With Tri-State Output