WS7812QD

Will Semiconductor Ltd.

9

Oct. 2017_V1.0

Register Description and Programming

Register

Parameter

Description

Default

Name (Binary)

Name

Address

(Hex)

Register_0

0000

MODE_CTRL

Bits[4:0]:

See Table B for logic

00000

Register_1

0001

MODE_CTRL

Bits[4:0]:

See Table A for logic

00000

RFFE_STATUS

001A

SOFTWARE RESET

Bits[7]:

Resets all data to default values except for

USID, GSID, or the

contents of the PM_TRIG Register.

0 = Normal operation (active)

1 =

Software reset

0

COMMAND_FRAME_PARITY_

ERR

Bit[6]:

Command sequence received with parity error

– discard command.

0

COMMAND_LENGTH_ERR

Bit[5]:

Command length error.

0

ADDRESS_FRAME_PARITY_E

RR

Bit[4]:

Address frame parity error =1.

0

DATA_FRAME_PARITY_ERR

Bit[3]:

Data frame with parity error.

0

READ_UNUSED_REG

Bit[2]:

Read command to an invalid address.

0

WRITE_UNUSED_REG

Bit[1]:

Write command to an invalid address.

0

BID_GID_ERR

Bit[0]:

Read command with a BROADCAST_ID (refer

to the MIPI Alliance

Specification)

or

GSID.

0

PM_TRIG

(Note 4)

001C

PWR_MODE

Bits[7:6]:

00 = Normal operation (active)

01 = Default settings (startup)

10 = Low power (low power)

11 = Reserved

00

Trigger_Mask_2

Bit[5]:

If this bit is set, trigger 2 is disabled. When all

triggers are disabled, if writing to a register that is

associated with trigger 2, the data goes directly to

the destination register.

0

Trigger_Mask_1

Bit[4]:

If this bit is set, trigger 1 is disabled. When all

triggers are disabled, if writing to a register that is

associated with trigger 1, the data goes directly to

the destination register.

0

Trigger_Mask_0

Bit[3]:

If this bit is set, trigger 0 is disabled. When all

triggers are disabled, if writing to a register that is

associated with trigger 0, the data goes directly to

the destination register.

0

Trigger_2

Bit[2]:

If this bit is set, data is loaded into the trigger 2

0