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PM25LD512 Datasheet(数据表) 3 Page - List of Unclassifed Manufacturers

部件型号  PM25LD512
说明  512Kbit/1 Mbit / 2 Mbit Single Operating Voltage Serial Flash Memory With 100 MHz Dual-Output SPI Bus
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制造商  ETC2 [List of Unclassifed Manufacturers]
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 3 page
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Pm25LD512/010/ 020
Confidential information
Chingis Technology Corp.
3
DRAFT Date: August, 2010, Rev:0.4
CONNECTION DIAGRAMS
5
6
7
8
1
2
3
4
Vcc
HOLD#
SCK
SIO
SO
GND
WP#
CE#
5
6
7
8
1
2
3
4
Vcc
HOLD#
SCK
SIO
SO
GND
WP#
CE#
PIN DESCRIPTIONS
SYMBOL
TYPE
DESCRIPTION
CE#
INPUT
Chip Enable: CE# low activates the devices internal circuitries for
device operation. CE# high deselects the devices and switches into
standby mode to reduce the power consumption. When a device is not
selected, data will not be accepted via the serial input pin (SlO), and the
serial output pin (SO) will remain in a high impedance state.
SCK
INPUT
Serial Data Clock
SIO
INPUT/OUTPUT
Serial Data Input/Output
SO
OUTPUT
Serial Data Output
GND
Ground
Vcc
Device Power Supply
WP#
INPUT
Write Protect: A hardware program/erase protection for all or part of a
memory array. When the WP# pin is low, memory array write-protection depends
on the setting of BP2, BP1 and BP0 bits in the Status Register. When the WP# is
high, the devices are not write-protected.
HOLD#
INPUT
Hold: Pause serial communication by the master device without resetting
the serial sequence.
CE#
CE#
SO
WP#
GND
Vcc
HOLD#
SCK
SIO
SIO
SCK
HOLD#
Vcc
SO
WP#
GND
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
8-Pin SOIC
8-Contact WSON
8-Pin TSSOP
8-Pin PDIP




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