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ALC888S-VD 数据表(PDF) 68 Page - Realtek Semiconductor Corp. |
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ALC888S-VD 数据表(HTML) 68 Page - Realtek Semiconductor Corp. |
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68 / 92 page  ALC888S-VD Datasheet 7.1+2 Channel HD Audio Codec with Two Independent SPDIF Outputs 60 Track ID: JATR-2265-11 Rev. 1.2 8.30. Verb – Set BEEP Generator (Verb ID=70Ah) Table 64. Verb – Set BEEP Generator (Verb ID= 70Ah) Set Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=01h Verb ID=70Ah Divider [7:0] 0’s for All Nodes ‘Divider’ in Set Command Bit Description 31:8 Reserved. 7:0 Frequency Divider, F[7:0]. The internal BEEP frequency is the result of dividing the 48kHz clock by 4 times the number specified in F[7:0]. The lowest tone is 48kHz/(255×4)=47Hz. The highest tone is 48kHz/(1×4)=12kHz. A value of 00h in F[7:0] disables the internal BEEP generator and allows external PCBEEP input. Note: All nodes except Audio Function Group (NID=01h) will ignore this verb. Codec Response for All NID Bit Description 31:0 0’s. 8.31. Verb – Get GPIO Data (Verb ID=F15h) Table 65. Verb – Get GPIO Data (Verb ID= F15h) Get Command Format Codec Response Format Bit [31:28] Bit [27:20] Bit [19:8] Payload Bit [7:0] Response [31:0] CAd=X Node ID=01h Verb ID=F15h 0’s 32-bit Response Codec Response for NID=01h (Audio Function Group) Bit Description 31:8 Reserved. 7:3 GPIO[7:2] Data. Not supported in the ALC888S-VD. 2:0 GPIO[1:0] Data. The value written (output) or sensed (input) on the corresponding pin if it is enabled. Codec Response for Other NID Bit Description 31:0 0’s. |
类似零件编号 - ALC888S-VD |
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类似说明 - ALC888S-VD |
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