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ALC5642R-VF-CG 数据表(PDF) 20 Page - Realtek Semiconductor Corp. |
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ALC5642R-VF-CG 数据表(HTML) 20 Page - Realtek Semiconductor Corp. |
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20 / 156 page  ALC5642-VF Datasheet Multi-Channel Audio Hub/CODEC with embedded Voice DSP and SounzReal TM Digital Sound Effect 8 Rev. 0.93 6. Pin Descriptions 6.1. Digital I/O Pins Table 1. Digital I/O Pins Name Type Pin Description Characteristic Definition DACDAT1 I 33 First I2S interface serial data input Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) ADCDAT1 O 34 First I2S interface serial data output VOL=0.1*DBVDD, VOH=0.9*DBVDD BCLK1 I/O 36 First I2S interface serial bit clock Master: VOL =0.1*DBVDD, VOH =0.9*DBVDD Slave: Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) LRCK1 I/O 35 First I2S interface synchronous signal Master: VOL =0.1*DBVDD, VOH =0.9*DBVDD Slave: Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) DACDAT2 I 31 Second I2S interface serial data input Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) ADCDAT2 O 32 Second I2S interface serial data output VOL=0.1*DBVDD, VOH=0.9*DBVDD BCLK2 I/O 30 Second I2S interface serial bit clock Master: VOL =0.1*DBVDD, VOH =0.9*DBVDD Slave: Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) LRCK2 I/O 29 Second I2S interface synchronous signal Master: VOL =0.1*DBVDD, VOH =0.9*DBVDD Slave: Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) SDA I/O 39 I2C interface serial data Open drain structure SCL I 38 I2C interface clock input Schmitt trigger MCLK I 37 I2S interface master clock input Schmitt trigger (VIL=0.35*DBVDD, VIH=0.65*DBVDD) GPIO1/IRQ I/O 40 General purpose input and output Interrupt output Output: VOL =0.1*DBVDD, VOH =0.9*DBVDD Input: Schmitt trigger GPIO2/ DMIC_SCL I/O 41 General purpose input and output Digital microphone clock output Output: VOL =0.1*DBVDD, VOH =0.9*DBVDD Input: Schmitt trigger LDO1_EN I 44 LDO1 enable control, for digital core power DCVDD Low: Disable, High: Enable Input threshold: VIL = 0.35*DBVDD VIH = 0.65*DBVDD Total: 14 Pins |
类似零件编号 - ALC5642R-VF-CG |
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类似说明 - ALC5642R-VF-CG |
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