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ALC5642R-VF-CG 数据表(PDF) 29 Page - Realtek Semiconductor Corp.

部件名 ALC5642R-VF-CG
功能描述  Multi-Channel Audio Hub/CODEC
Download  156 Pages
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制造商  REALTEK [Realtek Semiconductor Corp.]
网页  https://www.realtek.com/en/
标志 REALTEK - Realtek Semiconductor Corp.

ALC5642R-VF-CG 数据表(HTML) 29 Page - Realtek Semiconductor Corp.

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ALC5642-VF
Datasheet
Multi-Channel Audio Hub/CODEC with embedded Voice
DSP and SounzReal
TM Digital Sound Effect
17
Rev. 0.93
7.4.1.
Phase-Locked Loop
A Phase-Locked Loop (PLL) is used to provide a flexible input clock from 2.048MHz to 40MHz. The
source of the PLL can be set to MCLK, BCLK1 or BCLK2 by setting register.
The S/W driver can set up the PLL to output a frequency to match the requirement of system clock.
The PLL transmit formula as below:
FOUT = (MCLK * (N+2)) / ((M+2) * (K+2)) {Typical K=2}
Table 10.
Clock Setting Table for 48K (Unit: MHz)
MCLK
N
M
FVCO
K
FOUT
13
66
7
98.222
2
24.555
3.6864
78
1
98.304
2
24.576
2.048
94
0
98.304
2
24.576
4.096
70
1
98.304
2
24.576
12
80
8
98.4
2
24.6
15.36
81
11
98.068
2
24.517
16
78
11
98.462
2
24.615
19.2
80
14
98.4
2
24.6
19.68
78
14
98.4
2
24.6
24
39
8
98.4
2
24.6
Table 11.
Clock Setting Table for 44.1K (Unit: MHz)
MCLK
N
M
FVCO
K
FOUT
13
68
8
91
2
22.75
3.6864
72
1
90.931
2
22.733
2.048
86
0
90.112
2
22.528
4.096
64
1
90.112
2
22.528
12
66
7
90.667
2
22.667
15.36
63
9
90.764
2
22.691
16
66
10
90.667
2
22.667
19.2
64
12
90.514
2
22.629
19.68
67
13
90.528
2
22.632
24
62
15
90.352
2
22.588


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