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MC68020FC20 数据表(PDF) 4 Page - Motorola, Inc |
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MC68020FC20 数据表(HTML) 4 Page - Motorola, Inc |
4 / 306 page 9/29/95 SECTION 1: OVERVIEW UM Rev.1.0 viii M68020 USER’S MANUAL MOTOROLA TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 3.12 Power Supply Connections .....................................................................3-7 3.13 Signal Summary......................................................................................3-8 Section 4 On-Chip Cache Memory 4.1 On-Chip Cache Organization and Operation ..........................................4-1 4.2 Cache Reset ........................................................................................... 4-3 4.3 Cache Control .........................................................................................4-3 4.3.1 Cache Control Register (CACR) .........................................................4-3 4.3.2 Cache Address Register (CAAR) ........................................................4-4 Section 5 Bus Operation 5.1 Bus Transfer Signals............................................................................... 5-1 5.1.1 Bus Control Signals .............................................................................5-2 5.1.2 Address Bus ........................................................................................ 5-3 5.1.3 Address Strobe ....................................................................................5-3 5.1.4 Data Bus.............................................................................................. 5-3 5.1.5 Data Strobe ......................................................................................... 5-4 5.1.6 Data Buffer Enable ..............................................................................5-4 5.1.7 Bus Cycle Termination Signals............................................................5-4 5.2 Data Transfer Mechanism....................................................................... 5-5 5.2.1 Dynamic Bus Sizing ............................................................................5-5 5.2.2 Misaligned Operands...........................................................................5-14 5.2.3 Effects of Dynamic Bus Sizing and Operand Misalignment ................ 5-20 5.2.4 Address, Size, and Data Bus Relationships ........................................5-21 5.2.5 Cache Interactions ..............................................................................5-22 5.2.6 Bus Operation ..................................................................................... 5-24 5.2.7 Synchronous Operation with DSACK1/DSACK0 ............................... 5-24 5.3 Data Transfer Cycles ..............................................................................5-25 5.3.1 Read Cycle ..........................................................................................5-26 5.3.2 Write Cycle ..........................................................................................5-33 5.3.3 Read-Modify-Write Cycle.....................................................................5-39 5.4 CPU Space Cycles .................................................................................5-44 5.4.1 Interrupt Acknowledge Bus Cycles ......................................................5-45 5.4.1.1 Interrupt Acknowledge Cycle—Terminated Normally ...................... 5-45 5.4.1.2 Autovector Interrupt Acknowledge Cycle .........................................5-48 5.4.1.3 Spurious Interrupt Cycle .................................................................. 5-48 5.4.2 Breakpoint Acknowledge Cycle ...........................................................5-50 5.4.3 Coprocessor Communication Cycles .................................................. 5-53 5.5 Bus Exception Control Cycles................................................................. 5-53 5.5.1 Bus Errors ........................................................................................... 5-55 |
类似零件编号 - MC68020FC20 |
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类似说明 - MC68020FC20 |
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