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MC1GU064HCYB-0QC00 Datasheet(数据表) 44 Page - Samsung semiconductor

部件型号  MC1GU064HCYB-0QC00
说明  MultiMediaCard Specification
下载  66 Pages
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制造商  SAMSUNG [Samsung semiconductor]
网页  http://www.samsung.com/Products/Semiconductor
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MC1GU064HCYB-0QC00 Datasheet(HTML) 44 Page - Samsung semiconductor

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MultiMediaCard
TM
44
3 = stby
4 = tran
5 = data
6 = rcv
7 = prg
8 = dis
9–15 = reserved
8
EADY_FOR_DATA
SX
‘0’ = not ready
‘1’ = ready
corresponds to buffer empty signaling on
the bus
A
7:6
reserved
Permanently 0
5
APP_CMD
SR
‘0’ = disabled
‘1’ = enabled
The card will expect ACMD or indication
that the command has been interpreted
as ACMD.
C
4
reserved
Permanently 0
3:2
reserved for application specific commands
1:0
reserved for manufacturer test mode
4.9.8 Command Response Timings
All timing diagrams use the following schematics and abbreviations:
S
Start bit (= ‘0’)
T
Transmitter bit (Host = ‘1’, Card = ‘0’)
P
One-cycle pull-up (= ‘1’)
E
End bit (=1)
Z
High impedance state (-> = ‘1’)
D
Data bits
*
Repetition
CRC
Cyclic redundancy check bits (7 bits for command or
response, 16 bits for block data)
Card active
Host active
The difference between the P-bit and Z-bit is that a P-bit is actively driven to HIGH by the card
respectively host output driver, while Z-bit is driven to (respectively kept) HIGH by the pull-up resistors
RCMD respectively RDAT. Actively driven P-bits are less sensitive to noise superposition.
Timing Values
Min
Max
Unit
NCR
2
64
Clock cycles
NID
5
5
Clock cycles
NAC
2
10*(TAAC*Fop+1
00*NSAC)
Clock cycles
NRC
8
--
Clock cycles
NCC
8
--
Clock cycles
NWR
2
--
Clock cycles
NST
2
2
Clock cycles
The host command and the card response are clocked out with the rising edge of the host clock. The
delay between host command and card response is NCR clock cycles. The following timing diagram is
relevant for host command CMD3 :




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