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SM320C6202BGNY167 数据表(PDF) 65 Page - Texas Instruments |
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SM320C6202BGNY167 数据表(HTML) 65 Page - Texas Instruments |
65 / 83 page TMS320C6211, TMS320C6211B FIXED-POINT DIGITAL SIGNAL PROCESSORS SPRS073K − AUGUST 1998 − REVISED MARCH 2004 65 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 HOST-PORT INTERFACE TIMING (CONTINUED) 1st halfword 2nd halfword 5 17 8 6 5 17 8 5 15 9 16 15 9 7 4 3 2 1 2 1 2 1 2 1 2 1 2 1 HAS HCNTL[1:0] HR/W HHWIL HSTROBE† HCS HD[15:0] (output) HRDY (case 1) HRDY (case 2) 3 † HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 33. HPI Read Timing (HAS Not Used, Tied High) HAS† HCNTL[1:0] HR/W HHWIL HSTROBE‡ HCS HD[15:0] (output) HRDY (case 1) HRDY (case 2) 1st half-word 2nd half-word 5 17 8 20 5 17 8 5 15 9 16 15 9 7 4 3 11 10 11 10 11 10 11 10 11 10 11 10 19 19 18 18 † For correct operation, strobe the HAS signal only once per HSTROBE active cycle. ‡ HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS. Figure 34. HPI Read Timing (HAS Used) |
类似零件编号 - SM320C6202BGNY167 |
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类似说明 - SM320C6202BGNY167 |
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