ST 486 DX ASIC CORE

6/8

®

A range of bus master/bus slave/bus monitor

VHDL models are also available for high level 486

bus debug operations.

SYHTHESIS AND STATIC TIMING ANALYSIS

The Synopsys Design Compiler synthesis tool

family can be used for gate level synthesis and

static timing analysis. Interface to the back end

place and route engine allows for design specific

wire load models to be used during the synthesis

phase. Synopsys library views for the standard cell

libraries and high-level functional modules (such

as the ST486DX core) are used to perform static

timing analysis at block level, intra-block level and

at the top chip level.

Usage of Synopsys Test Compiler enables the

insertion

of full or partial scan and also IEEE

JTAG boundary scan insertion.

DELAY EVALUATION AND GATE LEVEL

SIMUATION

All cell timing information used for gate level

simulation and static timing analysis will be

generated by the SGS-Thomson proprietary delay

evaluator called EARLY. This suite of programs

evaluates

delays

using

operating

condition

information, input slope conditions and estimated

(pre-layout) parasitic capacitance or calculated

(post-layout) parasitic resistance and capacitance.

The output is in SDF format that can be annotated

into the gate level simulator and static timing

analysis tool.

Place and Route

This is performed on a module by module basis,

and then at the top level using the Cadence cell 3

layout tool. Interface to floorplanning tools (e.g.

Preview, ChipPlanner) will allow customisable wire

load models to be passed back to the synthesis

environment and also help in the reduction of

routing congestion which leads to smaller die size

and fewer iterations of the design post-layout.

RTL HDL

TES T CO MP ILE R

LOGIC SYNTHE SIS

FLOORPLAN

S YNOPSY S

SYNOPSY S

MANAG ER

GATE LEV EL SIMULATION

TSS I

BEHAVIOURA L

HDL

FLO OR PLANNING

BUS / MASTER MODEL

BUS FUNCTIONAL MODE L

MODEL SO URCE HARDWARE MO DEL

DELAY EVA LUATION AND

CLO CK TRE E SYNTHESIS

BLOCK LEVEL AND CHIP

LE VEL PLACE AND ROUTE

CELL 3

VHDL / Verilog

VHDL / Verilog

486 Views

Verilog Netlist

SDF

SDF

VHDL / Verilog

Wire Loads

& Placement data

VHDL/

Verilog

Co-simulation

Cadence

Leapfrog

Figure 4. Design Flow