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DAC5686IPZP 数据表(PDF) 5 Page - Texas Instruments

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部件名 DAC5686IPZP
功能描述  16-BIT, 500-MSPS, 2X16X INTERPOLATING DUAL-CHANNEL DIGITAL-TO-ANALOG CONVERTER
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制造商  TI [Texas Instruments]
网页  http://www.ti.com
标志 TI - Texas Instruments

DAC5686IPZP 数据表(HTML) 5 Page - Texas Instruments

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DAC5686
SLWS147B – APRIL 2003 – REVISED AUGUST 2004
DEVICE INFORMATION (continued)
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
BIASJ
13
I/O
Full-scale output current bias
CLK1
59
I
External clock input; data clock input
CLK1C
60
I
Complementary external clock input; data clock input
CLK2
62
I
External clock input; sample clock for the DAC (optional if PLL disabled)
CLK2C
63
I
Complementary external clock input; sample clock for the DAC (optional if PLL disabled)
CLKGND
58, 64
Ground return for internal clock buffer
CLKVDD
61
Internal clock buffer supply voltage
DA[15:0]
34–36,
I
A-channel data bits 0 through 15
39–43,
DA15 is most significant data bit (MSB).
48–55
DA0 is least significant data bit (LSB).
DB[0:15]
71–78,
I
B-channel data bits 0 through 15
83–87,
DB15 is most significant data bit (MSB).
90–92
DB0 is least significant data bit (LSB).
Note: The order of the B data bus can be reversed by register rev_bbus.
DGND
27, 38, 45,
Digital ground return
57, 69, 81,
88, 93, 99
DVDD
26, 32, 37,
Digital supply voltage
44, 56, 68,
82, 89, 100
EXTIO
11
I
Used as external reference input when internal reference is disabled (i.e., EXTLO connected to AVDD).
Used as internal reference output when EXTLO = AGND, requires a 0.1-
µF decoupling capacitor to
AGND when used as reference output
EXTLO
15
I
Internal reference ground. Connect to AVDD to disable the internal reference
IOUTA1
21
O
A-channel DAC current output. Full scale when all input bits are set to 1
IOUTA2
20
O
A-channel DAC complementary current output. Full scale when all input bits are set to 0
IOUTB1
5
O
B-channel DAC current output. Full scale when all input bits are set to 1
IOUTB2
6
O
B-channel DAC complementary current output. Full scale when all input bits are set to 0
IOGND
47, 79
Digital I/O ground return
IOVDD
46, 80
Digital I/O supply voltage
LPF
66
I/O
PLL loop filter connection. Can be left open or connected to GND if PLL is not used (PLLVDD = 0 V).
PHSTR
94
I
The PHSTR pin has two functions. When the sync_phstr register is 0, a high on the PHSTR pin resets
the NCO phase accumulator. When the sync_phstr register is 1, a PHSTR pin low-to-high transition
sets the divided clock phase in external clock mode, and a high on the PHSTR pin resets the NCO
phase accumulator.
PLLGND
65
Ground return for internal PLL
PLLVDD
67
PLL supply voltage. When PLLVDD is 0 V, the PLL is disabled.
PLLLOCK
70
O
PLL lock status bit. In PLL clock mode, PLLLOCK is high when PLL is locked to the input clock. In
external clock mode, PLLLOCK outputs the input rate clock.
QFLAG
98
O
Used in the interleaved data input mode: When the qflag register bit is 1, the QFLAG pin is used as an
output to identify the interleaved data sequence. QFLAG high identifies the data as channel B. Pin can
be left open when not used.
RESETB
95
I
Resets the chip when low
SCLK
29
I
Serial interface clock
SDENB
28
I
Active-low serial data enable, always an input to the DAC5686
SDIO
30
I/O
Bidirectional serial-port data in the three-pin serial interface mode. Input-only serial data in the four-pin
serial interface mode.
SDO
31
O
High-impedance state (the pin is not used) in the three-pin serial interface mode. Serial-port output data
in the four-pin serial interface mode.
SLEEP
96
I
Asynchronous hardware power-down input. Active high. Internal pulldown
TESTMODE
97
I
TESTMODE is DGND for the user.
5


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