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DS90UB962-Q1 数据表(PDF) 70 Page - Texas Instruments |
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DS90UB962-Q1 数据表(HTML) 70 Page - Texas Instruments |
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70 / 169 page  70 DS90UB962-Q1 SNLS573 – AUGUST 2018 www.ti.com Product Folder Links: DS90UB962-Q1 Submit Documentation Feedback Copyright © 2018, Texas Instruments Incorporated 7.6.1.11 SCL High Time Register The SCL High Time register field configures the high pulse width of the I2C SCL output when the Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4 additional oscillator clock periods. The internal oscillator has ±10% variation when REFCLK is not applied, which must be taken into account when setting the SCL High and Low Time registers. Table 29. SCL High Time Register (Address 0x0A) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 SCL_HIGH_TIME R/W 0x7A I2C Master SCL High Time This field configures the high pulse width of the SCL output when the Serializer is the Master on the local I2C bus. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL high time with the reference clock at 25 MHz + 100ppm. The delay includes 5 additional oscillator clock periods. Min_delay = 39.996ns * (SCL_HIGH_TIME + 5) 7.6.1.12 SCL Low Time Register The SCL Low Time register field configures the low pulse width of the SCL output when the serializer is the master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bidirectional control channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to approximately 100 kHz with the internal oscillator clock running at nominal 25 MHz. Delay includes 4 additional oscillator clock periods. The internal oscillator has ±10% variation when REFCLK is not applied, which must be taken into account when setting the SCL High and Low Time registers. Table 30. SCL Low Time Register (Address 0x0B) BIT FIELD TYPE DEFAULT DESCRIPTION 7:0 SCL_LOW_TIME R/W 0x7A I2C SCL Low Time This field configures the low pulse width of the SCL output when the Serializer is the Master on the local I2C bus. This value is also used as the SDA setup time by the I2C Slave for providing data prior to releasing SCL during accesses over the Bi-directional Control Channel. Units are 40 ns for the nominal oscillator clock frequency. The default value is set to provide a minimum 5us SCL low time with the reference clock at 25 MHz + 100ppm. The delay includes 5 additional clock periods. Min_delay = 39.996ns * (SCL_LOW_TIME+ 5) 7.6.1.13 RX_PORT_CTL Register Receiver port control register assigns rules for lock and pass in the general status register and allows for enabling and disabling each Rx port. Table 31. RX_PORT_CTL Register (Address 0x0C) BIT FIELD TYPE DEFAULT DESCRIPTION 7 BCC3_MAP R/W 0 Map Control Channel 3 to I2C Slave Port 0: I2C Slave Port 0 1: I2C Slave Port 1 6 BCC2_MAP R/W 0 Map Control Channel 2 to I2C Slave Port 0: I2C Slave Port 0 1: I2C Slave Port 1 5 BCC1_MAP R/W 0 Map Control Channel 1 to I2C Slave Port 0: I2C Slave Port 0 1: I2C Slave Port 1 4 BCC0_MAP R/W 0 Map Control Channel 0 to I2C Slave Port 0: I2C Slave Port 0 1: I2C Slave Port 1 |
类似零件编号 - DS90UB962-Q1 |
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类似说明 - DS90UB962-Q1 |
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