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DP83869HM 数据表(PDF) 31 Page - Texas Instruments

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部件名 DP83869HM
功能描述  High Immunity 10/100/1000 Ethernet Physical Layer Transceiver With Copper and Fiber Interface
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制造商  TI1 [Texas Instruments]
网页  http://www.ti.com
标志 TI1 - Texas Instruments

DP83869HM 数据表(HTML) 31 Page - Texas Instruments

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DP83869HM
www.ti.com
SNLS614 – SEPTEMBER 2018
Product Folder Links: DP83869HM
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Copyright © 2018, Texas Instruments Incorporated
9.4.4 Reduced GMII (RGMII)
The Reduced Gigabit Media Independent Interface (RGMII) is designed to reduce the number of pins required to
interconnect the MAC and PHY (12 pins for RGMII relative to 24 pins for GMII). To accomplish this goal, the data
paths and all associated control signals are reduced and are multiplexed. Both rising and trailing edges of the
clock are used. For Gigabit operation, the GTX_CLK and RX_CLK clocks are 125 MHz, and for 10- and 100-
Mbps operation, the clock frequencies are 2.5 MHz and 25 MHz, respectively.
For more information about RGMII timing, see the RGMII Interface Timing Budgets application report (SNLA243).
9.4.4.1 1000-Mbps Mode Operation
All RGMII signals are positive logic. The 8-bit data is multiplexed by taking advantage of both clock edges. The
lower 4 bits are latched on the positive clock edge and the upper 4 bits are latched on trailing clock edge. The
control signals are multiplexed into a single clock cycle using the same technique.
To reduce power consumption of RGMII interface, (TX_EN - TX_ERR) and (RX_DV - RX_ERR) are encoded in a
manner that minimizes transitions during normal network operation. TX_CTRL pin will denote TX_EN on rising
edge of GTX_CLK and will denote a logic derivative of TX_EN and TX_ERR on the falling edge of GTX_CLK.
RX_CTRL will denote RX_DV on rising edge of RX_CLK and will denote a logic derivative of RX_DV and
RX_ERR on the falling edge of RX_CLK. The encoding for the TX_ERR and RX_ERR is given in Equation 1 and
Equation 2:
TX_ERR = GMII_TX_ER (XOR) GMII_TX_EN
where
GMII_TX_ER and GMII_TX_EN are logical equivalent signals in GMII standard.
(1)
RX_ERR = GMII_RX_ER (XOR) GMII_RX_DV
where
GMII_RX_ER, and GMII_RX_DV are logical equivalent signals in GMII standard.
(2)
When receiving a valid frame with no error, RX_CTRL = True is generated as a logic high on the rising edge of
RX_CLK and RX_CTRL = False is generated as a logic high at the falling edge of RX_CLK. When no frame is
being received, RX_CTRL = False is generated as a logic low on the rising edge of RX_CLK and RX_CTRL =
False is generated as a logic low on the falling edge of RX_CLK.
The TX_CTRL is treated in a similar manner. During normal frame transmission, the signal stays at a logic high
for both edges of GTX_CLK and during the period between frames where no error is indicated, the signal stays
low for both edges.
9.4.4.2 1000-Mbps Mode Timing
The DP83869HM provides configurable clock skew for the GTX_CLK and RX_CLK to optimize timing across the
interface. The transmit and receive paths can be optimized independently. Both the transmit and receive path
support 16 programmable RGMII delay modes through register configuration.
The timing paths can either be configured for Aligned mode or Shift mode. In Aligned mode, no clock skew is
introduced. In Shift mode, the clock skew can be introduced in 0.5-ns increments or in 0.25-ns increments
(through register configuration). Configuration of the Aligned mode or Shift mode is accomplished through the
RGMII Control Register (RGMIICTL), address 0x0032. In Shift mode, the clock skew can be adjusted using the
RGMII Delay Control Register (RGMIIDCTL), address 0x0086.
9.4.4.3 10- and 100-Mbps Mode
When the RGMII interface is operating in the 100-Mbps mode, the Ethernet Media Independent Interface (MII) is
implemented by reducing the clock rate to 25 MHz. For 10-Mbps operation, the clock is further reduced to 2.5
MHz. In the RGMII 10/100 mode, the transmit clock RGMII TX_CLK is generated by the MAC and the receive
clock RGMII RX_CLK is generated by the PHY. During the packet receiving operation, the RGMII RX_CLK may
be stretched on either the positive or negative pulse to accommodate the transition from the free-running clock to
a data synchronous clock domain. When the speed of the PHY changes, a similar stretching of the positive or
negative pulses is allowed. No glitch is allowed on the clock signals during clock speed transitions.
This interface operates at 10- and 100-Mbps speeds the same way it does at 1000-Mbps mode with the
exception that the data may be duplicated on the falling edge of the appropriate clock.


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