NB7NPQ7022M

www.onsemi.com

3

Figure 2. UQFN16 Package Pinout (Top View)

A_TX−

A_TX+

B_RX−

B_RX+

12

11

10

9

A_RX−

A_RX+

B_TX−

B_TX+

1

2

3

4

5

6

7

8

13

14

15

16

Exposed

Pad EP

Table 1. PIN DESCRIPTION

Pin No. Pin Name

Type

Description

1

A_RX−

DIFF IN

Channel A Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC−coupled.

2

A_RX+

3

B_TX−

DIFF OUT Channel B Differential output for 5 / 10 Gbps USB signals. Must be externally AC−coupled.

4

B_TX+

5

VCC

POWER

3.3 V power supply. VCC pins must be externally connected to power supply to guarantee proper oper-

ation.

6

CTRL_B0 LVCMOS IN Pin B0 for control of Flat Gain settings on Channel B having internal 100 kW pull up and 200 kW pull

ed to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor

68 kW connected from pin to Ground. Refer Table 2 for the different settings.

7

CTRL_B1 LVCMOS IN Pin B1 for control of Equalization settings on Channel B having internal 100 kW pull up and 200 kW pull

ed to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor

68 kW connected from pin to Ground. Refer Table 2 for the different settings.

8

GND

GND

Reference Ground. GND pins must be externally connected to power supply ground to guarantee

proper operation.

9

B_RX+

DIFF IN

Channel B Differential input pair for 5 / 10 Gbps USB signals. Must be externally AC coupled.

10

B_RX−

11

A_TX+

DIFF OUT Channel A Differential output for 5 / 10 Gbps USB signals. Must be externally AC coupled.

12

A_TX−

13

VCC

POWER

3.3 V power supply. VCC pins must be externally connected to power supply to guarantee proper oper-

ation.

14

CTRL_A0 LVCMOS IN Pin A0 for control of Equalization settings on Channel A having internal 100 kW pull up and 200 kW pull

ed to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor

68 kW connected from pin to Ground. Refer Table 2 for the different settings.

15

CTRL_A1 LVCMOS IN Pin A1 for Control of Flat Gain settings on Channel A having internal 100 kW pull up and 200 kW pull

ed to Ground, FLOAT “F” where the pin is left floating (open) and Rext “R” where an external resistor

68 kW connected from pin to Ground. Refer Table 2 for the different settings.

16

GND

GND

Reference Ground. GND pins must be externally connected to power supply ground to guarantee

proper operation.

EP

GND

GND

Exposed pad (EP). EP on the package bottom is thermally connected to the die for improved heat

transfer out of the package. The pad is not electrically connected to the die, but is recommended to be

soldered to GND on the PC Board.