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NB3H5150-01 数据表(PDF) 12 Page - ON Semiconductor |
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NB3H5150-01 数据表(HTML) 12 Page - ON Semiconductor |
12 / 19 page NB3H5150−01 www.onsemi.com 12 Table 10. AC CHARACTERISTICS VDD = AVDDn = 3.3 V ±5% or 2.5 V ±5%; VDDO = 3.3V ±5% or 2.5 V ±5% or 1.8 V ±5%; GND = 0 V; TA = −40°C to 85°C (Note 13) Symbol Unit Max Typ Min Characteristic tjit( F) Additive RMS Phase Jitter (PLL Bypass in I2C Mode) Integration Range:12 kHz − 5 MHz fout = 25 MHz, CLK1 LVCMOS 50 fs tpd Input to Output Propagation Delay (PLL Bypass in I2C Mode) 25 MHz 5 ns PSRR Ripple Induced Phase Spur Level 100 kHz & 1 MHz, 100 mVpp, Ripple Injected on VDD/AVDDn ≤ 100 MHz −60 dBc tr /tf Output Rise/Fall Times (CLKnA/CLKnB), 20% − 80% of VDDOn fout = 156.25 MHz LVPECL fout = 33.33 MHz @ VDDO = 3.3 V LVCMOS – 5 pF 120 500 200 800 300 1000 ps VINPP Input Voltage Swing (Differential Configuration) (Note 14) 100 1200 mV Stabilization Time Stabilization Time From Power−up VDD = 3.3 V to First Edge Out Upon Reprogram – (Pin−Strap mode), Change of Configuration Power−up to Static Output Levels – (Pin−Strap mode) Power−up to I2C Ready 5 3 1 5 6 3 ms tPWRDWN Time to Power Down, SCL/PD Low−to−High 50 100 200 ms Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product per- formance may not be indicated by the Electrical Characteristics if operated under different conditions. NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. 13. Measured by using a 25 MHz crystal as clock source. All LVPECL outputs are loaded with an external RL = 50 W to VDDO – 2 V (Figure 9); LVCMOS outputs loaded with RS = 33 W, CL = 5 pF, 5” 50 W trace, (Figure 11). 14. Input and output voltage swings are single−ended measurements operating in a differential mode. 15. VDD = 3.3 V, VDDO = 2.5 V (LVPECL) or 1.8 V (LVCMOS). Figure 3. Differential Input Driven Single−Ended Figure 4. Differential Inputs Driven Differentially Figure 5. Vth Diagram Figure 6. Differential Inputs Driven Differentially CLK_XTAL1 VDD GND VIH VIHmin VIHmax Vthmax Vth Vth Vthmin CLK_XTAL1 CLK_XTAL2 Vth Vth CLK_XTAL1 CLK_XTAL2 VILmax VIL VILmin VIHD VILD VID = |VIHD(CLK) − VILD(CLK)| CLK_XTAL1 CLK_XTAL2 VIH VIL |
类似零件编号 - NB3H5150-01_17 |
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类似说明 - NB3H5150-01_17 |
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