MT9045

Data Sheet

5

Zarlink Semiconductor Inc.

Functional Description

The MT9045 is a Multitrunk System Synchronizer, providing timing (clock) and synchronization (frame) signals to

interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which

is described in the following sections.

Reference Select MUX Circuit

The MT9045 accepts two simultaneous reference input signals and operates on their falling edges. Either the

primary reference (PRI) signal or the secondary reference (SEC) signal can be selected as input to the TIE

Corrector Circuit. The selection is based on the Control, Mode and Reference Selection of the device. See Table 1

and Table 4.

Frequency Select MUX Circuit

The MT9045 operates with one of four possible input reference frequencies (8kHz, 1.544MHz, 2.048MHz or

19.44MHz). The frequency select inputs (FS1 and FS2) determine which of the

four frequencies may be used at

the reference inputs (PRI and SEC). Both inputs must have the same frequency applied to them. A reset (RST)

must be performed after every frequency select input change. See Table 1.

Table 1 - Input Frequency Selection

Time Interval Error (TIE) Corrector Circuit

The TIE corrector circuit, when enabled, prevents a step change in phase on the input reference signals (PRI or

SEC) from causing a step change in phase at the input of the DPLL block of Figure 1.

During reference input rearrangement, such as during a switch from the primary reference (PRI) to the secondary

reference (SEC), a step change in phase on the input signals will occur. A phase step at the input of the DPLL

would lead to unacceptable phase changes in the output signal.

44

TDO

Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling

edge of TCK. This pin is held in high impedance state when JTAG scan is not enable.

45

TDI

Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin.

46

TRST

Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the

Test-Logic-Reset state. If not used, this pin should be held low.

47

TCK

Test Clock (Input): Provides the clock to the JTAG test logic. This pin is internally pulled up to

48

TMS

Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP

FS2

FS1

Input Frequency

0

0

19.44MHz

01

8kHz

1

0

1.544MHz

1

1

2.048MHz

Pin Description (continued)

Pin #

Name

Description