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MT46V256M4 数据表(PDF) 16 Page - Micron Technology |
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MT46V256M4 数据表(HTML) 16 Page - Micron Technology |
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16 / 74 page  1Gb: x4, x8, x16 DDR SDRAM PRELIMINARY 09005aef8076894f Micron Technology, Inc., reserves the right to change products or specifications without notice. 1gbDDRx4x8x16_2.fm - Rev. A 3/03 EN 16 ©2003 Micron Technology. Inc. DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected. NO OPERATION (NOP) The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# is LOW with RAS#, CAS#, and WE# equal HIGH). This prevents unwanted commands from being regis- tered during idle or wait states. Operations already in progress are not affected. LOAD MODE REGISTER The mode registers are loaded via inputs A0–A13. See mode register descriptions in the Register Defini- tion section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a sub- sequent executable command cannot be issued until tMRD is met. ACTIVE The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A13 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A pre- charge command must be issued before opening a dif- ferent row in the same bank. READ The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai (where i = 9 for x16; 9, 11 for x8; or 9, 11, 12 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. WRITE The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–Ai (where i = 9 for x16; 9, 11 for x8; or 9, 11, 12 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coinci- dent with the data. If a given DM signal is registered LOW, the corresponding data will be written to mem- ory; if the DM signal is registered HIGH, the corre- sponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location. PRECHARGE The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not inter- rupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 deter- mines whether one or all banks are to be precharged, and in the case where only one bank is to be pre- charged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. Auto Precharge Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable auto pre- charge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is auto- matically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual Read or Write command. This device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Auto precharge ensures that the precharge is initi- ated at the earliest valid stage within a burst. This “ear- liest valid stage” is determined as if an explicit PRECHARGE command was issued at the earliest pos- sible time, without violating tRAS (MIN), as described |
类似零件编号 - MT46V256M4 |
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类似说明 - MT46V256M4 |
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