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MT46V256M4 数据表(PDF) 1 Page - Micron Technology

部件名 MT46V256M4
功能描述  DOUBLE DATA RATE (DDR) SDRAM
Download  74 Pages
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT46V256M4 数据表(HTML) 1 Page - Micron Technology

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PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
09005aef8076894f
1gbBDDRx4x8x16_1.fm - Rev. A 3/03 EN
1
©2003 Micron Technology, Inc.
1Gb: x4, x8, x16
DDR SDRAM
PRELIMINARY
DOUBLE DATA RATE
(DDR) SDRAM
MT46V256M4 – 64 MEG X 4 X 4 BANKS
MT46V128M8 – 32 MEG X 8 X 4 BANKS
MT46V64M16 – 16 MEG X 16 X 4 BANKS
For the latest data sheet revisions, please refer to the
Micron Web site: www.micron.com/datasheets
Features
•VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two
–one per byte)
• Programmable burst lengths: 2, 4, or 8
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
• Concurrent auto precharge option is supported
tRAS lockout supported (tRAP = tRCD)
NOTE:
1. Supports PC2100 modules with 2.5-3-3 timing
2. Supports PC1600 modules with 2-2-2 timing,
* Minimum clock rate @ CL= 2.5
** CL = CAS (Read) Latency
OPTIONS
MARKING
• Configuration
256 Meg x 4 (64 Meg x 4 x 4 banks)
256M4
128 Meg x 8 (32 Meg x 8 x 4 banks)
128M8
64 Meg x 16 (16 Meg x 16 x 4 banks)
64M16
•Plastic Package – OCPL
66-pin TSOP(400 mil width, 0.65mm
pin pitch)
TG
66-pin TSOP Lead-Free (400 mil width,
0.65mm pin pitch)
P
• Timing – Cycle Time
7.5ns @ CL = 2.5 (DDR266B)1, 2
-75
• Temperature Rating
Commercial Temperature
(0
°C to +70°C)
None
Key Timing Parameters
SPEED
GRADE
CLOCKRATE
DATA-OUT
WINDOW*
ACCESS
WINDOW
DQS–DQ
SKEW
CL=2**
CL=2.5**
-75
100 MHz
133MHz
2.5ns
±0.75ns
+0.5ns
256 MEG X 4 128 MEG X 8 64 MEG X 16
Configuration
64 Meg x 4 x 4
banks
32 Meg x 8 x 4
banks
16 Meg x 16 x 4
banks
Refresh Count
8K
8K
8K
Row Addressing
16K (A0–A13)
16K (A0–A13)
16K (A0–A13)
Bank Addressing
4(BA0,BA1)
4(BA0,BA1)
4(BA0,BA1)
Column Addressing
4K(A0–A9,
A11, A12)
2K(A0–A9, A11)
1K(A0–A9)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
NC
VSSQ
UDQS
DNU
VREF
VSS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x16
VDD
DQ0
VDDQ
DQ1
DQ2
VssQ
DQ3
DQ4
VDDQ
DQ5
DQ6
VssQ
DQ7
NC
VDD
Q
LDQS
A13
VDD
DNU
LDM
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x16
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
NC
DQ5
VSSQ
NC
DQ4
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
x8
x4
VSS
NC
VSSQ
NC
DQ3
VDDQ
NC
NC
VSSQ
NC
DQ2
VDDQ
NC
NC
VSSQ
DQS
DNU
VREF
VSS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
VSS
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
NC
DQ2
VDDQ
NC
DQ3
VSSQ
NC
NC
VDDQ
NC
A13
VDD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
x8
x4
VDD
NC
VDDQ
NC
DQ0
VSSQ
NC
NC
VDDQ
NC
DQ1
VSSQ
NC
NC
VDDQ
NC
A13
VDD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
VDD
Figure 1: Pin Assignment (Top View)
66-pin TSOP


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