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LTC2230CUP 数据表(PDF) 1 Page - Linear Technology

部件名 LTC2230CUP
功能描述  Electrical Specifications Subject to Change
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制造商  LINER [Linear Technology]
网页  http://www.linear.com
标志 LINER - Linear Technology

LTC2230CUP 数据表(HTML) 1 Page - Linear Technology

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LTC2230/LTC2231
1
22301p
Wireless and Wired Broadband Communication
Cable Head-End Systems
Power Amplifier Linearization
Communications Test Equipment
FEATURES
DESCRIPTIO
APPLICATIO S
TYPICAL APPLICATIO
Sample Rate: 170Msps/135 Msps
61dB SNR up to 140MHz Input
75dB SFDR up to 200MHz Input
775MHz Full Power Bandwidth S/H
Single 3.3V Supply
Low Power Dissipation: 890mW/660mW
LVDS, CMOS, or Demultiplexed CMOS Outputs
Selectable Input Ranges: ±0.5V or ±1V
No Missing Codes
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
Data Ready Output Clock
Pin Compatible Family
170Msps: LTC2220 (12-Bit), LTC2230 (10-Bit)
135Msps: LTC2221 (12-Bit), LTC2231 (10-Bit)
64-Pin 9mm x 9mmQFN Package
10-Bit,170Msps/
135Msps ADCs
The LTC
®2230 and LTC2231 are 170Msps/135Msps, sam-
pling 10-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. The LTC2230/
LTC2231 are perfect for demanding communications
applications with AC performance that includes 61dB SNR
and 75dB spurious free dynamic range for signals
up to 200MHz. Ultralow jitter of 0.15psRMS allows
undersampling of IF frequencies with excellent noise
performance.
DC specs include ±0.2LSB INL (typ), ±0.1LSB DNL (typ)
and no missing codes over temperature. The transition
noise is a low 0.12LSBRMS.
The digital outputs can be either differential LVDS, or
single-ended CMOS. There are three format options for
the CMOS outputs: a single bus running at the full data rate
or two demultiplexed buses running at half data rate with
either interleaved or simultaneous update. A separate
output power supply allows the CMOS output swing to
range from 0.5V to 3.3V.
The ENC+ and ENCinputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL, or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
, LTC and LT are registered trademarks of Linear Technology Corporation.
+
INPUT
S/H
CORRECTION
LOGIC
OUTPUT
DRIVERS
10-BIT
PIPELINED
ADC CORE
CLOCK/DUTY
CYCLE
CONTROL
FLEXIBLE
REFERENCE
D9
D0
ENCODE INPUT
REFH
REFL
ANALOG
INPUT
22301 TA01
CMOS
OR
LVDS
3.3V
VDD
OVDD
OGND
0.5V
TO 3.3V
INPUT FREQUENCY (MHz)
0
90
85
80
75
70
65
60
55
50
45
40
600
100
400
200
2230 TA01b
500
300
4th OR HIGHER
2nd OR 3rd
SFDR vs Input Frequency
Electrical Specifications Subject to Change


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