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LFX1200B-03F900I 数据表(PDF) 7 Page - Lattice Semiconductor |
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LFX1200B-03F900I 数据表(HTML) 7 Page - Lattice Semiconductor |
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7 / 89 page  Lattice Semiconductor ispXPGA Family Data Sheet 7 Figure 4. LUT in Shift Register Mode Carry Chain Generator The Carry Chain Generator is useful for implementing high-speed arithmetic functions. The CCG consists of a two- input XOR gate whose carryout can be cascaded with the input of the adjacent CCG. As shown in Figure 5, the carryin signal feeds CLE3 of the PFU and is propagated through CLE2 and CLE1 before reaching CLE0. The sum output of the CCG can be fed to the CSE through the WLG. The carryout must propagate to CLE0 for use outside the PFU. The carryout from the PFU can feed the W0 input of CSE0. The CCG also helps to effectively implement wider functions by using its logic elements to expand the capabilities of the LUT-4. Figure 5. Carry Chain Generator Wide Logic Generator The WLG contains the logic necessary to implement wide gate functions. This is made up of a set of multiplexers that are located between the CLE and the CSE. The WLG helps in enhancing the wide gating capability of the PFU. The outputs of each CLE can be cascaded in the WLG to build wide gating functions. Wide multiplexing functions are also possible with a similar use of the WLG. Figure 6 illustrates the WLG. LUT-4 PFUCLK0 SHIFTOUT (4A) SEL (SHIFTIN) CEB0 A B CIN COUT SUM CLE3 CLE1 CLE2 CLE0 SUM3 COUT(r,c) COUT to CSE0 CIN from Routing COUT(r+1,c) SUM2 SUM1 SUM0 |
类似零件编号 - LFX1200B-03F900I |
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类似说明 - LFX1200B-03F900I |
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