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ADRF6510 数据表(PDF) 22 Page - Analog Devices |
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ADRF6510 数据表(HTML) 22 Page - Analog Devices |
22 / 32 page ADRF6510 Data Sheet Rev. B | Page 22 of 32 0 –80 –70 –60 –50 –40 –30 –20 –10 0 10 PIN (dBm) –5 –10 –15 –20 –25 –30 –40 –35 –50 –45 750mV p-p 1.50V p-p 1.75V p-p 2.00V p-p 2.25V p-p 2.90V p-p 2.95V p-p Figure 52. EVM vs. RF Input Power over Output Voltage Levels, IF = 5 MHz, OFDS Pulled High Figure 52 shows EVM degradation as the signal level nears compression. At 2.25 V p-p the signal is already degraded a few decibels. When the output level is near the absolute limits of the output stage, the EVM becomes much more erratic over the RF input power level. EFFECT OF COFS ON EVM When enabled, the dc offset compensation loop effectively nulls any information below the high-pass corner set by the COFS capacitor. However, loss of the low frequency information of the modulated signal can degrade the EVM in some cases. As the signal bandwidth becomes larger, the percentage of information that is corrupted by the high-pass corner becomes smaller. In such cases, it is important to select a COFS capacitor large enough to minimize the high-pass corner frequency, which prevents loss of information and degraded EVM. Figure 53 shows the effect of COFS values at a single signal bandwidth of 6.75 MHz = 1.35 × 5 MHz over input power. Figure 54 shows that EVM can be improved by using a bigger COFS value and/or increasing the signal bandwidth. Increasing signal bandwidth will improve EVM to a point after which the bandwidth limitations of the source, the part, and/or the receiver will start to dominate and degrade EVM. 0 –80 –70 –60 –50 –40 –30 –20 –10 0 10 PIN (dBm) –5 –10 –15 –20 –25 –30 –40 –35 –50 –45 COFS = 1µF COFS = 100nF COFS = 1nF Figure 53. EVM vs. RF Input Power over COFS Values 0 0 35 30 25 20 15 10 5 SIGNAL BANDWIDTH (MHz) –5 –10 –15 –20 –25 –30 –40 –35 –45 COFS = 1µF COFS = 100nF COFS = 1nF Figure 54. EVM vs. Signal BW over COFS Values ANTI-ALIASING FILTER The noise spectral density of the ADRF6510 outside the filter bandwidth is limited by the fixed VGA output noise. It may be necessary to use an external, fixed-frequency, passive filter prior to an analog-to-digital conversion to prevent noise aliasing from degrading the signal-to-noise ratio. As shown in Figure 47 and Figure 48, the noise density at higher frequencies tends to be flat, and any higher IF noise aliasing into the Nyquist zone has minimal effects. When designing an antialiasing filter, it is necessary to consider the overall source and load impedance presented by the ADRF6510 and the ADC input to design the filter network. The differential baseband output impedance of the ADRF6510 is 20 Ω and is designed to drive a high impedance ADC input. It may be desirable to terminate the ADC input to a lower imped- ance by using a terminating resistor, such as 500 Ω. The terminating resistor helps to better define the input impedance at the ADC input at the cost of a slightly reduced gain. The order and type of filter network depend on the desired high frequency rejection required, the pass-band ripple, and the group delay. Filter design tables provide outlines for various filter types and orders, illustrating the normalized inductor and capacitor values for a 1 Hz cutoff frequency and 1 Ω load. After scaling the normalized prototype element values by the actual desired cutoff frequency and load impedance, the series reactance elements are halved to realize the final balanced filter network component values. As an example, a second-order Butterworth, low-pass filter design is shown in Figure 55 where the differential load impedance is 500 Ω and the source impedance is 50 Ω. The normalized series inductor value for the 10-to-1, load-to-source impedance ratio is 0.074 H, and the normalized shunt capacitor is 14.814 F. For a 31 MHz cutoff frequency, the single-ended equivalent circuit consists of a 0.191 µH series inductor followed by a 152 pF shunt capacitor. |
类似零件编号 - ADRF6510_17 |
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类似说明 - ADRF6510_17 |
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