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MT46H8M16LF 数据表(PDF) 1 Page - Micron Technology

部件名 MT46H8M16LF
功能描述  Mobile Double Data Rate (DDR) SDRAM
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制造商  MICRON [Micron Technology]
网页  http://www.micron.com
标志 MICRON - Micron Technology

MT46H8M16LF 数据表(HTML) 1 Page - Micron Technology

  MT46H8M16LF Datasheet HTML 1Page - Micron Technology MT46H8M16LF Datasheet HTML 2Page - Micron Technology MT46H8M16LF Datasheet HTML 3Page - Micron Technology  
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128Mb: 8 Meg x 16 Mobile DDR SDRAM
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PDF: 09005aef818ff781/Source: 09005aef818ff799
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT46H8M16.fm - Rev. A 03/05 EN
1
©2005 Micron Technology, Inc. All rights reserved.
‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron
to meet Micron’s production data sheet specifications.
Mobile Double Data Rate (DDR) SDRAM
MT46H8M16LF – 2 Meg x 16 x 4 Banks
For a complete data sheet, please refer to www.micron.com/mobileds.
Features
•VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V
• Bidirectional data strobe per byte of data (DQS)
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Four internal banks for concurrent operation
• Data masks (DM) for masking write data–one mask
per byte
• Programmable burst lengths: 2, 4, or 8
• Concurrent auto precharge option is supported
• Auto refresh and self refresh modes
• 1.8V LVCMOS compatible inputs
• On-chip temperature sensor to control refresh rate
• Partial array self refresh (PASR)
• Selectable output drive (DS)
• Clock stop capability
Options
Marking
•VDD/VDDQ
• 1.8V/1.8V
H
• Configuration
• 8 Meg x 16 (2 Meg x 16 x 4 banks)
8M16
•Plastic Package
• 60-Ball VFBGA (Lead-Free)
8mm x 10mm
CF
• Timing – Cycle Time
• 7.5ns @ CL = 3
• 10ns @ CL = 3
-6
-10
• Operating Temperature Range
• Commercial (0° to +70°C)
• Industrial (-40°C to +85°C)
None
IT
Figure 1: 60-Ball VFBGA Assignment
(Top View)
Table 1:
Configuration Addressing
Architecture
8 Meg x 16
Configuration
2 Meg x 16 x 4
Refresh Count
4K
Row Addressing
4K (A0–A11)
Bank Addressing
4 (BA0, BA1)
Column Addressing
1K (A0–A9)
Table 2:
Key Timing Parameters
Speed
Grade
Clock Rate
Data-Out
Window
Access
Time
DQS-DQ
Skew
CL = 3
CL = 2
-75
133 MHz
-
2ns
6.0s
+0.6ns
-10
104 MHz
-
2.8ns
7.0ns
+0.7ns
-75
-
83 MHz
4ns
6.5ns
+0.6ns
-10
67 MHz
5ns
7.0ns
+0.7ns
1234
6
789
5
A
B
C
D
E
F
G
H
J
K
VSSQ
DQ14
DQ12
DQ10
DQ8
NC
CK#
A12/NC
A8
A5
VSS
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CKE
A9
A6
VSS
DQ15
DQ13
DQ11
DQ9
UDQS
UDM
CK
A11
A7
A4
VDDQ
DQ1
DQ3
DQ5
DQ7
NC
WE#
CS#
A10/AP
A2
DQ0
DQ2
DQ4
DQ6
LDQS
LDM
CAS#
BA0
A0
A3
VDD
VSSQ
VDDQ
VSSQ
VDDQ
VDD
RAS#
BA1
A1
VDD


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