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MKL04Z32VFK4 数据表(PDF) 8 Page - NXP Semiconductors |
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MKL04Z32VFK4 数据表(HTML) 8 Page - NXP Semiconductors |
8 / 49 page Table 7. Voltage and current operating behaviors (continued) Symbol Description Min. Max. Unit Notes VOL Output low voltage — High drive pad • 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA • 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA — — 0.5 0.5 V V 1 IOLT Output low current total for all ports — 100 mA IIN Input leakage current (per pin) for full temperature range — 1 μA 3 IIN Input leakage current (per pin) at 25 °C — 0.025 μA 3 IIN Input leakage current (total all pins) for full temperature range — 41 μA 3 IOZ Hi-Z (off-state) leakage current (per pin) — 1 μA RPU Internal pullup resistors 20 50 k Ω 4 1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. 2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When configured as a GPIO output, it acts as a pseudo open drain output. 3. Measured at VDD = 3.6 V 4. Measured at VDD supply voltage = VDD min and Vinput = VSS 2.2.4 Power mode transition operating behaviors All specifications except tPOR and VLLSx→RUN recovery times in the following table assume this clock configuration: • CPU and system clocks = 48 MHz • Bus and flash clock = 24 MHz • FEI clock mode POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz. Table 8. Power mode transition operating behaviors Symbol Description Min. Typ. Max. Unit tPOR After a POR event, amount of time from the point VDD reaches 1.8 V to execution of the first instruction across the operating temperature range of the chip. — — 300 μs 1 • VLLS0 → RUN — 95 115 μs • VLLS1 → RUN Table continues on the next page... General 8 Kinetis KL04 32 KB Flash, Rev4 03/2014. Freescale Semiconductor, Inc. |
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