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ISL97687 数据表(PDF) 6 Page - Renesas Technology Corp |
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ISL97687 数据表(HTML) 6 Page - Renesas Technology Corp |
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6 / 24 page  ISL97687 FN7714 Rev.3.00 Page 6 of 24 Sep 13, 2017 Absolute Maximum Ratings (T A = +25°C) Thermal Information VIN, EN, PWMI, ACTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 45V VDC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.75V COMP, ISET1, ISET2, PWM_SET, OSC, CS, OVP. . . . . . . . . . . . . . . . . . . . . . .-0.3V to min (VDC+0.3V, 5.75V) EN_VSYNC, CSEL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V STV, EN_ADIM, EN_PS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 5.75V CH1 - CH4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 75V GD, SLEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 18V PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V Above voltage ratings are all with respect to AGND pin ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V Charged Device Model (JESD22-C101E) . . . . . . . . . . . . . . . . . . . . . . . 1kV Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA Thermal Resistance JA (°C/W) JC (°C/W) 28 Ld TQFN (4 layer + vias, Notes 5, 6) . . . 32 4 28 Ld SOIC (4 layer, Notes 7, 8) . . . . . . . . . 54 25 Thermal Characterization (Typical, Note 9) PSIJT (°C/W) 28 Ld TQFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 28 Ld SOIC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Maximum Continuous Junction Temperature . . . . . . . . . . . . . . . . .+125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Power Dissipation TQFN (W) SOIC (W) TA < +25°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.13 1.85 TA < +70°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.72 1.02 TA < +85°C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.25 0.74 TA < +105°C . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.63 0.37 Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For JC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. For JC, the “case temp” location is taken at the package top center. 8. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 9. PSIJT is the PSI junction-to-top thermal characterization parameter. If the package top temperature can be measured with this rating then the die junction temperature can be estimated more accurately than the JC and JC thermal resistance ratings. Electrical Specifications All specifications below are characterized at T A = -40°C to +105°C; VIN = 12V, EN = 5V. Boldface limits apply over the operating temperature range, -40°C to +105°C. PARAMETER DESCRIPTION CONDITION MIN (Note 10)TYP MAX (Note 10)UNIT GENERAL VIN Backlight Supply Voltage (Note 11) 932 V IVIN_STBY VIN Shutdown Current EN = 0 5 µA IVIN_ACTIVE Switching RFPWM = 3.3kΩ, ILED = 100mA, fSW = 600kHz, COUT_SW = 1nF 10 13 mA Non-switching 4 5.5 mA VUVLO Undervoltage Lock-out Threshold 2.9 3.3 V VUVLO_HYS Undervoltage Lock-out Hysteresis 300 mV LINEAR REGULATOR VDC 5V Analog Bias Regulator VIN > 6V 4.8 5 5.1 V VDC_DROP VDC LDO Load Regulation Tolerance IVDC = 30mA 71 100 mV VLOGIC 2.5V Logic Bias Regulator VIN > 6V 2.3 2.4 2.5 V VLOGIC_DROP VLOGIC LDO Load Regulation Tolerance IVLOGIC = 30mA 31 100 mV BOOST SWITCH CONTROLLER tSS Soft-Start 16 ms ISW_LIMIT Boost FET Current Limit (See Equation 5)RSENSE = 50mΩ 3.1 3.4 3.8 A tR Gate Rise Time COUT_SW = 1000pF 20 ns tF Gate Falling Time COUT_SW = 1000pF 17.6 ns VGD Gate Driver Output Voltage COUT_SW = 1000pF 10 V |
类似零件编号 - ISL97687 |
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类似说明 - ISL97687 |
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