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ADSP-21364SKBC-ENG 数据表(PDF) 5 Page - Analog Devices |
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ADSP-21364SKBC-ENG 数据表(HTML) 5 Page - Analog Devices |
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5 / 52 page  ADSP-21364 Preliminary Technical Data Rev. PrB | Page 5 of 52 | September 2004 signal processing, and are commonly used in digital filters and Fourier transforms. The two DAGs of the ADSP-21364 contain sufficient registers to allow the creation of up to 32 circular buff- ers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce over- head, increase performance, and simplify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21364 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetch- ing up to four 32-bit values from memory—all in a single instruction. ADSP-21364 MEMORY AND I/O INTERFACE FEATURES The ADSP-21364 adds the following architectural features to the SIMD SHARC family core. On-Chip Memory The ADSP-21364 contains three megabits of internal SRAM. Each block can be configured for different combinations of code and data storage (see Table 2 on Page 5). Each memory block supports single-cycle, independent accesses by the core proces- sor and I/O processor. The ADSP-21364 memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a sin- gle cycle. The ADSP-21364’s, SRAM can be configured as a maximum of 96K words of 32-bit data, 192K words of 16-bit data, 64K words of 48-bit instructions (or 40-bit data), or combinations of differ- ent word sizes up to three megabits. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float- ing-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point for- mats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Table 2. ADSP-21364 Internal Memory Space IOP Registers 0x0000 0000 – 0003 FFFF Long Word (64 bits) Extended Precision Normal or Instruction Word (48 bits) Normal Word (32 bits) Short Word (16 bits) BLOCK 0 ROM 0x0004 0000– 0x0004 7FFF BLOCK 0 ROM 0x0008 0000–0x0008 AAAA BLOCK 0 ROM 0x0008 0000– 0x0008 FFFF BLOCK 0 ROM 0x0010 0000–0x0011 FFFF Reserved 0x0004 8000–0x0004 BFFF Reserved 0x0009 0000–0x0009 7FFF Reserved 0x0012 0000–0x0012 FFFF BLOCK 0 RAM 0x0004 C000–0x0004 FFFF BLOCK 0 RAM 0x0009 0000–0x0009 5555 BLOCK 0 RAM 0x0009 8000–0x0009 FFFF BLOCK 0 RAM 0x0013 0000–0x0013 FFFF BLOCK 1 ROM 0x0005 0000–0x0005 7FFF BLOCK 1 ROM 0x000A 0000–0x000A AAAA BLOCK 1 ROM 0x000A 0000– 0x000A FFFF BLOCK 1 ROM 0x0014 0000–0x0015 FFFF Reserved 0x0005 8000–0x0005 BFFF Reserved 0x000B 0000–0x000B 7FFF Reserved 0x0016 0000–0x0016 FFFF BLOCK 1 RAM 0x0005 C000–0x0005 FFFF BLOCK 1 RAM 0x000B 0000–0x000B 5555 BLOCK 1 RAM 0x000B 8000–0x000B FFFF BLOCK 1 RAM 0x0017 0000–0x0017 FFFF BLOCK 2 RAM 0x0006 0000–0x0006 1FFF BLOCK 2 RAM 0x000C 0000–0x000C 2AAA BLOCK 2 RAM 0x000C 0000–0x000C 3FFF BLOCK 2 RAM 0x0018 0000–0x0018 7FFF Reserved 0x0006 2000–0x0006 FFFF Reserved 0x000C 4000– 0x000D FFFF Reserved 0x0018 8000–0x001B FFFF BLOCK 3 RAM 0x0007 0000–0x0007 1FFF BLOCK 3 RAM 0x000E 0000–0x000E 2AAA BLOCK 3 RAM 0x000E 0000–0x000E 3FFF BLOCK 3 RAM 0x001C 0000–0x001C 7FFF Reserved 0x0007 2000–0x0007 FFFF Reserved 0x000E 4000–0x000F FFFF Reserved 0x001C 8000–0x001F FFFF Reserved 0x0020 0000–0xFFFF FFFF |
类似零件编号 - ADSP-21364SKBC-ENG |
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类似说明 - ADSP-21364SKBC-ENG |
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